ASIC Functional Test Engineering Intern

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

ASIC Functional Test (AFT) Engineering Intern

As an ASIC Functional Test (AFT) Engineering Intern, you will join our Hardware Ops team to develop, automate, and execute system-level functional tests on d-Matrix’s Corsair and next-generation silicon. AFT is our board-level test discipline: a single ASIC is seated in a socket on a custom Validation Board (EVB) equipped with thermal control heads, programmable power delivery, sideband control interfaces, and high-speed I/O stimulus—giving you full observability and controllability of the device under test.

Your primary mission: build and extend the Python-based automation infrastructure that orchestrates AFT test sequences, controls sideband interfaces, manages thermal profiles, collects data, and generates pass/fail verdicts—turning what would be manual bench work into repeatable, scalable, production-grade test flows.

• Develop and extend Python-based test automation frameworks that orchestrate end-to-end AFT sequences on the EVB—from power-on initialization through functional test execution to data logging and verdict generation.

• Write / Modify control scripts for sideband interfaces (I²C, SPI, JTAG, UART, GPIO) to configure device registers, apply stimulus, toggle modes, and read back status during test.

• Automate thermal profiling workflows: script the temperature control heads to sweep across defined thermal corners (cold/room/hot), trigger test sequences at each setpoint, and aggregate results across temperature.

• Build automation for power sequencing and supply margining—scripting programmable power supplies to step through voltage corners while running functional tests and capturing current measurements.

• Create robust logging, data collection, and result-parsing pipelines that automatically tag test runs with device ID, EVB configuration, thermal/voltage conditions, firmware version, and pass/fail outcomes.

• Integrate automation with version control (Git) and CI workflows so test scripts are traceable, peer-reviewed, and regression-tested before deployment.

• Execute and debug functional test sequences on the EVB with a single ASIC socketed, validating chip functionality across boot, firmware load, DIMC core operation, memory subsystem checks, and PCIe link training.

• Bring up and validate new EVB revisions—verifying socket contact integrity, power rail stability, signal quality on high-speed interfaces, and thermal head calibration.

• Run sideband-controlled test modes (BIST, scan, functional patterns) by driving sideband commands from Python scripts and verifying expected device responses.

• Reproduce and isolate failure modes reported from production or characterization, using the EVB’s full debug access (JTAG, trace ports, register dumps) to localize issues.

• Analyze AFT results across device populations to identify systematic failure signatures, voltage/temperature sensitivities, and outlier patterns using pandas, NumPy, and matplotlib.

• Build automated reports and dashboards that surface test coverage metrics, pass rates by test block, and failure Pareto charts for product and design engineering teams.

• Support root-cause and failure analysis (RCFA) by correlating AFT data with silicon lot, design revision, and packaging parameters.

• Collaborate with the manufacturing and operations teams to transition proven AFT automation from the lab into production-floor workflows.

• Document test procedures, automation APIs, and EVB setup guides so your work scales beyond the internship.

• Present findings and recommendations to engineering leadership through clear, data-backed presentations.

• Currently pursuing a M.S. in Electrical Engineering, Computer Engineering, or a closely related field.

• Strong Python programming skills - you should be comfortable writing production-quality scripts that control hardware, parse data, and run unattended. Experience with pandas, NumPy, matplotlib, or similar data/analysis libraries.

• Comfort with hardware-software interaction—you’ve written code that talks to real devices over serial, I²C, SPI, JTAG, UART, or GPIO (even in a lab class or personal project).

• Solid fundamentals in digital circuits and ASIC concepts—you understand clock domains, reset sequences, register access, scan/BIST basics, and why functional test matters beyond structural test.

• Hands-on lab aptitude—you’re not afraid to socket a chip, hook up probes, read a schematic, or debug a board-level issue.

• Familiarity with scripting for automation—writing tools that orchestrate multi-step hardware workflows, parse logs, move data between systems, and generate reports.

• Ability to work on-site in Santa Clara, CA 3–5 days per week for the duration of the 12-week internship.

• Experience with EVB/board-level bring-up or debug—power rail validation, signal integrity checks, or JTAG-based debug on FPGA or ASIC platforms.

• Familiarity with lab instruments (oscilloscopes, logic analyzers, signal generators, programmable power supplies, thermal chambers) and scripting their control via SCPI/VISA or vendor APIs.

• Experience with test automation frameworks (pytest, Robot Framework, or custom hardware test harnesses) and CI tools (Jenkins, GitLab CI).

• Experience with embedded firmware concepts—boot sequences, firmware loading, register map interaction, sideband protocols.

• Prior internship or co-op in semiconductor test, silicon validation, hardware bring-up, or a related discipline.

• Familiarity with PCIe, LPDDR, or high-speed SerDes link training and debug at the board level.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.