Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Logic Synthesis CAD engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As Logic Synthesis Computer Aided Design (CAD) engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our products have industry-leading power, performance and area.

Minimum qualifications

• BS degree in Electrical Engineering or Computer Science
• Five years of experience in synthesis flows - either in a design or CAD role
• Expertise in industry-standard front-end implementation tools
• Proficiency in at least one of the following scripting languages - Tcl, Perl and Python

Preferred qualifications

• MS degree in Electrical Engineering or Computer Science
• Ten years of hands-on experience in synthesis and implementation of high-performance chips - either in a design or CAD role
• Knowledge of logic design and hardware description languages (Verilog and SystemVerilog)
• Deep expertise in industry-standard synthesis tools (Design Compiler or Genus)
• Expertise in industry-standard logic equivalence tools (Formality or LEC)
• Knowledge of DFT - scan insertion, BIST etc
• High level of proficiency in Tcl as well as one of either Perl or Python
• Experience with automation (Eg. Makefiles)
• Proven track record of managing and regressing front-end implementation flows

Roles and Responsibilities

• Develop, integrate and release new features in the synthesis, logic equivalence and constraints flows
• Develop, integrate and release in-house custom CAD tools, flows and scripts
• Work with cross-functional teams - RTL design, physical design, DFT and methodology teams to define HDL coding guidelines and best-practices
• Maintain and support front-end implementation flows, and work with physical design teams to resolve project-specific issues
• Aid in timing debug and constraint definition
• Recommend methodology improvements to ensure our silicon has the best power, performance and area
• Work with vendors to resolve tool issues