Join the most cutting-edge and well-funded startup in Silicon Valley as a Coherent Fabric Micro-architecture and RTL Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Coherent Fabric Micro-architect/Design Engineer, you will work with chip architects to conceive of the micro-architecture and deliver RTL design for a coherent home node. You will also help with architecture/product definition of the SoC through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
• 5+ years of practical experience with implementation coherent fabric/protocols for scalable, multi-core SOCs

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Expertise in implementation of snoop filter or directory based coherent fabrics
• Expertise in the design of coherent, high speed cache controllers 
• Strong understanding of ordering rules in a multi-core system
• Strong understanding of fabric topologies and related performance issues 
• Experience with multi-socket coherency is a plus
• Expertise in CHI and other AMBA protocols is a plus
• Familiarity with high performance and low power design techniques
• Some experience in design verification and/or physical design is a plus

Roles and Responsibilities

• Work with chip architect to understand architecture concept and high level requirements
• Develop the micro-architecture and write design specifications for a coherent fabric including the home node, snoop filter, caches, etc.
• Convert design spec to Verilog RTL
• Support the verification team to devise appropriate test plans and verification strategy
• Collaborate with physical design team to close timing, area targets, reliability, etc