Join the most cutting-edge and well-funded startup in Silicon Valley as a DFT Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Senior DFT, you will work with chip architects, chip designers, implementation engineers and test engineers to define the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you’ll insure it becomes reality. We’re doing a grounds up implementation of a new chip architecture, so you’ll have to ability to affect a new design.

Minimum qualifications

• BA/BS degree in Electrical/Computer Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC test, DFT, and debug
• 5+ years of practical experience with test or DFT

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Hands-on expertise with commercial test generation tools for large complex designs
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST
• Experience with RTL simulation, synthesis and back end implementation flows
• Experience defining and implementing MBIST engines
• Experience running test compression software
• Lab and test floor experience with real silicon
• Experience trading off test options with product performance and schedule requirements
• Experience creating and releasing full test programs for device screening
• Yield estimation and test optimization

Roles and Responsibilities

• Define DFT strategy and methodologies
• Define test structures, debug structures, test plans
• Create test vectors or oversee their creation
• Collaborate with physical design team to close requirements
• Validate DFT requirements are being met
• Work with designers to increase test coverage, debug observability and flexibility
• Verify post-PD designs meet DFT requirements
• Work with test personnel, stepping in to do run tests when needed