Join the most cutting-edge and well-funded hardware startup in Silicon Valley as the lead engineer responsible for power management of a complex SOC. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Power Management Architect, you will work with chip architects to conceive of the system level macro-architecture and chip level micro-architecture of an efficient and high performance compute SoC. Your input will drive the product definition through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 7 years of practical experience designing power management systems in successfully shipped, high volume products
• Strong fundamentals in digital ASIC design and power of CMOS circuits
• Experience in power delivery systems including multi-phase bucks and LDOs

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Knowledge of SOC architecture
• Familiarity with high performance and low power design techniques
• Knowledge of major SOC interfaces like PCIE, DRAM, coherent socket to socket interfaces and PMIC to SOC links
• Experience in power and performance telemetry
• Experience in TDP (thermal design power) capping and control
• Experience in measurement and management of over-current and voltage droop events

Role and Responsibilities

• Work with chip architect to understand architecture concept and high level system requirements
• Define the control system that drives power state control and transitions (FSM and/or micro controller based)
• Define overall clocking scheme of major SOC blocks and chip interfaces
• Participate in the definition of the boot up sequence
• Define the communication protocol between processor SOC and the PMIC
• Define power rails and power states for all major functional blocks
• Define SOC level TDP power estimation and capping methodology
• Must have good communication skills and able to work in dynamic environment with top level engineers and technologists