Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Physical Design Clock Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to create best in class clocking solutions for SoC. 

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Experience in all aspects of construction and analysis of low skew and low power clock generation and distribution. 
• Experience in clock H-tree, mesh, spines and CTS implementations. Good understanding of device physics, RC delay and electrical aspects. 

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Experience in chip physical design, standard cell optimizations and clock construction.
• Experience in defining clock methodology across different designs. 
• Experience in deep submicron process technology nodes is strongly preferred. 
• Experience PLL specifications, clock skew estimation and jitter measurements. 
• Good communication skills to work with different teams to accurately describe issues and follow them through for completion. 

Roles and Responsibilities

• Work with design teams to understand, implement and validate SoC clocking.
• Drive overall clock generation and distribution methodology on the chip.
• Work with CAD & block level designers to implement the clocking techniques for optimizing skew and power.
• Perform jitter analysis and measurements and provide feedback to block level and top level physical design engineers on key fixes required.