Physical Design Timing Engineer

| South Bay
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Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Physical Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure.

Minimum qualifications

  • BA/BS degree in Electrical Engineering with 5+ years of practical experience
  • Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. 
  • Knowledge of all aspects of timing including noise, cross-talk and others.
  • Knowledge of basic SoC architecture and HDL languages like Verilog.

Preferred qualifications

  • MS degree in Electrical Engineering; 10 years of practical experience
  • Experience in timing flows with industry standard tools. 
  • Experience in all aspects of timing closure for multi-clock domain designs. 
  • Experience in deep submicron process technology nodes is strongly preferred. 
  • Experience with STA on large SOC with multi-scenario timing closure.
  • Experience with Timing ECO techniques and implementation.
  • Knowledge of library cells and optimizations.
  • Familiar with circuit modeling, transistor fundamentals and worst case corner selection. 
  • Solid understanding industry standard tools for synthesis, place & route and tapeout flows.
  • Good communication skills to work with different teams to accurately describe issues and follow them through for completion.

Roles and Responsibilities

  • Work with design and DFT teams to understand, implement and validate constraints.
  • Run SOC timing runs at all hierarchies
  • Analyze timing and work with RTL/DFT teams to facilitate logic changes required.
  • Feedback to block level and top level physical design engineers on key fixes required for timing closure. 
  • Work with CAD team to implement timing infrastructure.
  • Create ECOs from timing runs to help timing closure. 
  • Document and help with timing methodology definition.

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Location

Our company is located near the Mission College campus. With ample restaurants, shops and a movie theater walking distance from the entrance.

An Insider's view of NUVIA Inc.

What are some social events your company does?

I love how open, friendly and supportive everyone is at NUVIA. A few of my favorite things about working here are the virtual happy hours to help employees get to know each other better, many of whom have never met in person due to the pandemic, and the focus on health and wellness with virtual exercise classes offered multiple times a week.

Anupama

SoC Design Verification engineer

What does your typical day look like?

The underpinnings of the NUVIA team is the shared commitment we all have to challenge the status quo. NUVIA is a place where candidates are carefully chosen not just for their best-in-class technical talent but also for sharing the same passion, insatiable desire and innovative spirit to go off and do something extraordinary.

Sriram

Product Marketing Lead

What are NUVIA Inc. Perks + Benefits

Health Insurance & Wellness Benefits
Dental Benefits
Vision Benefits
Health Insurance Benefits
Team workouts
NUVIA offers multiple virtual workout classes a week for employees to attend while working from home during the pandemic.
Retirement & Stock Options Benefits
401(K)
Vacation & Time Off Benefits
Paid Holidays
Perks & Discounts
Casual Dress
Happy Hours
Currently we host happy hours virtually.
Professional Development Benefits
Lunch and learns
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