Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Physical Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Physical Design Engineer, you will work with microarchitecture, RTL design and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows. 

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Experience with Synthesis, place and route and signoff timing/power analysis
• Knowledge of all aspects of physical construction, integration, physical and electrical verification 
• Knowledge of basic SoC architecture and HDL languages like Verilog.

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Experience in developing and implementing power grid and clock specifications
• Experience in all aspects of timing closure for multi-clock domain designs
• Experience in deep submicron process technology nodes is strongly preferred
• Knowledge of library cells and optimizations
• Solid understanding industry standard tools for synthesis, place & route and tapeout flows
• Solid understanding of physical design verification methods to debug LVS/DRC. 

Roles and Responsibilities

• Perform block level implementation using place and route techniques to meet area/timing and power requirements
• Create floorplan with pin placement, partitions and power grid
• Generate block level static timing constraints
• Perform Synthesis, Place & Route on the designs using industry standard tools and deliver GDS
• Validate the designs for functional and electrical robustness
• Generate and implement ECOs to fix noise, timing and EM/IR violations
• Involve in defining correct by construction physical design methodologies.