Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a SOC Debug RTL Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a SOC Debug RTL Design Engineer, you will work with chip architects to conceive of the SOC debug micro-architecture, implement the micro-architecture and also help with architecture/product definition through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
• 5+ years of practical experience in implementing SOC debug and trace features

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Experience with ARM Coresight architecture and implementation
• Experience with implementing SOC debug units like PMU, ETM, ELA, DAP, ATB, STM, etc.
• Experience implementing SOC subsystems including its debug and trace features
• Strong understanding of IO interfaces for debug like JTAG, SWD, HSIF, USB etc.
• Strong understanding of debug SW tool chains
• Knowledge of SOC architecture
• Familiarity with high performance and low power design techniques
• Some hands-on experience in design verification and/or physical design
• Understanding of debug authorization, lifecycle management and related security issues are plus

Roles and Responsibilities

• Work with chip architect to understand architecture concept and high level requirements
• Conceive of the micro-architecture and write design specifications
• Convert design spec to Verilog RTL
• Provide assertions for the design to ensure RTL is of the highest quality
• Support the verification team to devise appropriate test plans and verification strategy
• Collaborate with physical design team to close timing, area targets, reliability, etc
• Assist in silicon bring-up, debug and characterization