Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a SOC Modeling Lead. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

We believe that a competitive product starts with a thorough analysis via architecture modeling. As a SOC Performance Architect, you will be creating performance and power models for the fabrics / memory controller / IO, validating the models, conducting detailed studies and working with architects to shape the SoC design.

Minimum qualifications

• MS in Computer Science/Computer Engineering/Electrical Engineer with 3 years of experience in SoC performance/power modeling
• Strong grasp of the fundamentals of interconnects, traffic QoS, distributed caches, coherency flows, memory controller, PCIe flows
• Proficient in C++ and Perl / Python
• Ability to independently identify, troubleshoot and solve problems

Preferred qualifications

• MS in Computer Science/Computer Engineering/Electrical Engineer with 6 years of experience in SoC performance/power modeling
• Familiarity with AMBA bus protocols such as AXI, CHI
• Familiarity with DRAM protocols such as LPDDR5, DDR5
• Familiarity with IO protocols such as PCIe, CXL, CCIX

Role and Responsibilities

• Develop a SoC performance/power model that encompasses blocks such as interconnects, distributed caches, memory controllers, IO controllers
• Verify model correctness by writing unit-tests and debugging mismatches against expectations
• Use model to conduct detailed studies and identify avenues for improving the SoC’s performance/power characteristics
• Work with architects, RTL developers to productize the improvements identified through detailed studies 
• Continually refine the model to match the RTL design
• Verify that the model correlates with RTL, which may involve creating a verification plan, writing directed tests and checkers