Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Virtual Platform Design Lead. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Virtual Platform Design Lead, you will work with the Software, SOC Design, and SOC Design Verification teams to develop transactional models of the SOC and surrounding system to enable accelerated software development and verification. In this role, you will be responsible for defining the virtual platform, developing and integrating models for SOC components and working with the Software and Design Verification teams on integration and debugging.

Minimum qualifications

• BS/MS/PhD in Computer Engineering/Electrical Engineering with more than 5 years experience in SOC modeling, instruction set simulator development, or development of SW/HW simulation environments
• Strong understanding of computer architecture concepts
• Skillful at debugging the hardware/software interface for OSes and device drivers
• Proficient in C, C++ and scripting languages such as Python
• Ability to independently identify, troubleshoot and solve problems using HW and SW debugging tools

Preferred qualifications

• Familiarity with simulators such as Fast Models, Virtualizer, Virtual System Platform, QEMU
• Proficient in SystemC, Verilog, and System Verilog, and Assembly
• Familiarity with industry standard technologies like AXI, PCIe, DDR, TrustZone
• Experience with RTL simulators such as Cadence Xcelium, Synopsys VCS
• MS degree in Computer Engineering/Electrical Engineering; 10 years of practical experience
• Automated simulator test development and integration experience
• Understanding of software unit and integration test methodologies

Roles and Responsibilities

• Develop the virtual platform system, both creating new models as well as integrating third party models
• Collaborate with software team on bring up and automated testing
• Partner with SOC Design and Design Verification teams on defining model behaviors and verifying equivalency to RTL
• Influence the long term strategy for co-development and co-verification including hybrid simulation methodologies