Physical Design Engineer

About the Role:

As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow — from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).

Key Responsibilities:

• Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.

• Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.

• Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.

• Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.

• Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.

• Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.

• Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.

Salary Range

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:

• Hands-on digital/SoC physical design (synthesis through P&R and sign-off).

• Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.

• Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.

• Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.

• Power/IR analysis, signal/power integrity reporting, and corrective action planning.

• Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.

Preferred Qualifications:

• Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.

• Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.

• Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.

• Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.

• Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.

• Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.