Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a Coherent IO Micro-architecture and RTL Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a Coherent IO Micro-architect and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture and deliver RTL design for the IO bridge to the coherent fabric. You will also help with architecture/product definition of the SOC through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
• Strong understanding of PCIe and one or more coherent IO protocols like CCIX and CXL.

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• 5+ years of practical experience with implementation of coherent interconnects/protocols
• Strong understanding of ordering rules for various protocols and experience with bridging across protocols
• Expertise in multi-socket interconnect implementations like GMI (Infinity Fabric), QPI/UPI, CCIX, etc.
• Strong understanding of IO performance issues from protocol level to application level 
• Experience in IOMMU design and/or performance analysis 
• Experience in designing IO link controllers for PCIe or other high speed interfaces is a plus
• Expertise in CHI and other AMBA protocols is a plus
• Familiarity with high performance and low power design techniques
• Some experience in design verification and/or physical design is a plus

Roles and Responsibilities

• Work with chip architect to understand architecture concept and high level requirements
• Develop the micro-architecture and write design specifications for the Coherent IO bridge interfacing with the rest of the coherent fabric
• Convert design spec to Verilog RTL
• Support the verification team to devise appropriate test plans and verification strategy
• Collaborate with physical design team to close timing, area targets, reliability, etc