Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a High Speed IO Controller RTL Design Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a High Speed IO Controller RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture and deliver RTL design for the IO controllers interfacing with high speed Serdes PHYs. You will also help with architecture/product definition of the SOC through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
• Experience in micro-architecture and/or design of the controller for at least one of the high speed Serdes interfaces like PCIe, Ethernet, Die2Die, etc.

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• 5+ years of practical experience with implementation of the transaction layer, data link layer, and/or the logical physical layer including PCS
• Expertise in implementation of ordering, buffering and flow control logic
• Strong understanding of link management and training requirements including power state management
• Expertise in implementation of RAS features like FEC, CRC and replay features
• Experience implementing controllers for a multi-protocol PHY is a plus
• Strong understanding of PIPE interface requirements is highly desired
• Strong understanding of IO performance issues from protocol level to application level 
• Familiarity with high performance and low power design techniques
• Some experience in design verification and/or physical design is a plus

Roles and Responsibilities

• Work with Fabric designers and Serdes PHY designers to define optimal interfaces 
• Develop the micro-architecture and write design specifications for a high speed IO controller factoring in the SoC architecture requirements
• Convert design spec to Verilog RTL
• Support the verification team to devise appropriate test plans and verification strategy
• Collaborate with physical design team to close timing, area targets, reliability, etc