Join the most cutting-edge and well-funded hardware startup in Silicon Valley as a SOC Security HW Engineer. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

As a SOC Security HW Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

Minimum qualifications

• BA/BS degree in Electrical Engineering with 5+ years of practical experience
• Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
• Experience with ASIC design/micro-architecture, synthesis, timing/power analysis
• Experience in design and/or integration of Cryptographic HW blocks

Preferred qualifications

• MS degree in Electrical Engineering; 10 years of practical experience
• Knowledge of SOC architecture and security infrastructure
• Knowledge of cryptographic algorithms and protocols
• Familiarity with HW and SW attacks and countermeasures
• Familiarity with high performance and low power design techniques
• Some hands-on experience in design verification and/or physical design
• Knowledge of FPGA and emulation platforms
• Knowledge of assertion-based formal verification
• Domain knowledge in one or more of these areas: secure boot, secure debug, MMU, memory protection, HW access control

Roles and Responsibilities

• Work with chip architect to understand architecture concept and high level requirements
• Conceive of the micro-architecture and write design specifications
• Convert design spec to Verilog RTL
• Provide assertions for the design to ensure RTL is of the highest quality
• Support the verification team to devise appropriate test plans and verification strategy
• Collaborate with physical design team to close timing, area targets, reliability, etc
• Collaborate with power team on power analysis and closure
• Assist in emulation, FPGA, prototyping efforts
• Assist in silicon bring-up, debug and characterization