Jobs at Arrow Electronics, Inc.

Implement and verify DFT for advanced-node (3nm/5nm) SoCs: scan insertion, ATPG (compressed/uncompressed), pattern simulation, MBIST insertion/verification, JTAG insertion, silicon bring-up, scripting and flow automation, and debug using Verdi/VCS.

Design and verify ASIC RTL using Verilog/SystemVerilog, EDA flows and industry interfaces (PCIe, AXI/APB). Develop scripts, apply low-power UPF, CDC and STA techniques, and use Fusion Compiler/Design Compiler toolchains. Collaborate with customers and report progress while ensuring design signoff and timing closure.

Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.

Lead post-silicon validation for ML accelerators from RTL/emulation through silicon bring-up and production. Develop validation strategies, execute complex functional/performance/power tests, debug hardware in lab, build CI/CD and automated test infrastructure, validate ML workloads, and collaborate across architecture, design, firmware, and software teams to drive root cause analysis and production deployment.

Design and implement DFT (scan, MBIST, ATPG), verify test patterns via gate‑level simulations, perform post‑silicon diagnosis, and collaborate with synthesis, STA, physical design, and test engineers to debug DFT issues and bring up test vectors on silicon. Automate flows using TCL and use Tessent/Synopsys tools for implementation and verification.