Jobs at Arrow Electronics, Inc.

Perform board bring-up and hardware-software integration on Qualcomm QCS platforms. Develop and customize BSPs, Linux kernel, device trees, and drivers; debug bootloader/kernel/platform issues; validate hardware, integrate peripherals, and optimize system stability, performance, and power. Collaborate with hardware, firmware, and product teams.

Provides network lab, infrastructure, systems administration, and testbed engineering support. Configures and troubleshoots Cisco routers, switches, servers, optical modules, and fiber connectivity; manages Linux-based deployments and network services; develops Python automation; and supports SONiC, AI/ML, GPU, high-density, and multi-rack environments. Performs infrastructure benchmarking, troubleshooting, and deployment across on-site client facilities.

Develop and customize BSPs, Linux kernels, device drivers, and embedded systems for Qualcomm QCS hardware. Perform board bring-up, hardware-software integration, validation, and debugging of bootloaders, kernels, peripherals, and platform issues. Collaborate with hardware, firmware, and product engineering teams to optimize system stability, performance, and power consumption. The role requires Embedded Linux, C/C++, Qualcomm QCS, ARM, ITAR compliance, and strong debugging skills.

Senior design verification engineer responsible for system-level verification using SystemVerilog/UVM and C/C++ testbenches. Duties include testplan development, building BFM/driver/monitor/scoreboard components, stress and corner testing, failure debug, assertions, coverage closure, gate-level simulations, and customer reporting.

Perform DO-178C SOI-2 certification reviews and author/verify system, high-level, and low-level requirements for TSN/networking software. Evaluate architecture, design, traceability, coding standards, and compliance for safety-critical avionics, collaborating with software, systems, FPGA, and certification teams.

Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, and design-quality closure through CDC, lint, and RDC checks. Communicates project progress to customers, supports process improvements, resolves complex problems independently, and provides informal guidance to junior staff.

Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Responsibilities include fabric generation, synthesis, timing constraints, floor-planning considerations, performance optimization, register integration, CDC, lint, RDC, and design-quality closure. The engineer independently resolves complex problems, supports junior staff, improves processes, and communicates progress and technical status to customers.