Jobs at Etched

Lead the Node Systems team developing host software, system configurations, rack interfaces, diagnostics, and performance optimizations for large-scale inference clusters. Set technical direction, mentor engineers, debug hardware/software interactions, and partner with hardware, firmware, manufacturing, test, fleet software, and inference teams. Drive systems work across scheduling, memory, networking, accelerator communication, simulation, platform bring-up, validation, and production deployment while remaining hands-on with architecture, code, profiling, and debugging.

Lead and scale Etched’s legal function, including team development, legal operations, contract processes, automation, complex commercial negotiations, corporate governance, financings, and IPO preparation. Advise executives and the board on strategic transactions, equity, compliance, intellectual property, employment, and disputes. Manage legal budgets and outside counsel while partnering with engineering, manufacturing, finance, and commercial teams across U.S. and international operations.

Manage end-to-end semiconductor production planning, scheduling, capacity forecasting, procurement, supplier coordination, and logistics across wafers, packaging, assembly, and test. Partner with foundries, OSATs, engineering, validation, and internal operations teams to support engineering builds and mass-production ramp. Build forecasts, dashboards, and executive reports while mitigating supply, test infrastructure, and manufacturing bottlenecks.

Build AI agents that autonomously design, simulate, evaluate, and improve electrical and mechanical hardware from requirements through manufacturable outputs. Integrate CAD, EDA, and simulation tools; develop engineering representations, evaluations, datasets, feedback systems, and reproducible experiment infrastructure. Collaborate with electrical, mechanical, and manufacturing teams to ship agent-generated designs and measure improvements in design cycle time, hardware performance, and engineering effort.

Lead Etched’s physical-world brand experiences, including conferences, recruiting events, product launches, investor events, internal gatherings, and speaker programs. Own events end to end across creative direction, production, logistics, vendors, budgets, and measurement. Partner with founders, creatives, recruiters, engineers, agencies, and external partners to deliver polished, memorable experiences aligned with recruiting, brand, and business goals.

As an RTL Intern, you will design microarchitecture and implement logic in Verilog, contribute to RTL development, and engage in the design cycle.

Support People Operations and Legal through compliance audits, employee records review, filings, contracts, onboarding and offboarding, recruiting handoffs, process documentation, and cross-functional company projects. The intern will investigate discrepancies, organize sensitive information, research requirements, coordinate across teams, and drive time-sensitive operational work to completion in a fully in-person San Jose office.

Build and deploy production-level solutions for Etched’s critical engineering challenges. Projects may include internal hardware tools, manufacturing execution systems, or agentic AI systems for R&D. The intern will own a project from scoping through production, working across full-stack engineering, infrastructure, and product development in a fast-paced, ambiguous environment.

Designs complex IC substrate packages for high-power AI processors and accelerators, including large multilayer layouts, dense routing, power delivery networks, and signaling beyond 50GHz. The role optimizes CoWoS interposer designs, performs DRC and LVS verification, collaborates with silicon, SI/PI, packaging, and manufacturing teams, and supports design reviews and technical guidance for junior engineers.

Manage and maintain Allegro schematic symbol and PCB footprint libraries. Create, validate, and organize accurate, manufacturable ECAD components; maintain metadata, part numbering, approvals, and datasheet links. Collaborate with electrical, layout, manufacturing, and supplier teams to resolve library issues, meet IPC, JEDEC, and DFM requirements, and improve fabrication yield. Perform quality checks and use version control and SKILL scripting to preserve data integrity and automate library tasks.

Design and validate power delivery networks for high-current ASIC systems: perform PDN pre/post-layout analysis, DC IR-drop and AC impedance simulations, VRM modeling, thermal co-simulation, DRC/PI checks, bring-up debug, and maintain simulation-to-hardware correlation.

The Technical Program Manager will oversee program delivery, align teams, manage vendor relationships, and optimize processes in the Infrastructure organization.

Lead technical accounting and external financial reporting: implement ASC 606/IFRS 15 revenue policies, own NetSuite ARM implementation, draft technical memos, advise on inventory, warranty, equity reporting, prepare external statements and disclosures, strengthen controls, and build/manage a revenue/technical accounting team.

The Electrical Engineer will lead schematic design for accelerator modules, collaborate on system requirements, and manage documentation and testing for hardware systems.

The internship involves hands-on product design, development of design infrastructure, and system integration for high power ASIC systems, focusing on mechanical and electrical engineering aspects.

Provide end-to-end IT support for engineering and operations, manage endpoints and MDM/MAM, administer identity and access (SSO/IAM), design and secure networks (VPNs, VLANs, firewalls), implement EDR/XDR, automate workflows (Python/Bash/PowerShell), and coordinate vendors to maintain high operational reliability and compliance.

Build and maintain automation, CI/CD, and observability for hybrid cloud and on-prem HPC workflows. Optimize Slurm scheduling, manage containerized environments, integrate cloud resources, implement caching/artifact systems, and support security, secrets management, and developer productivity across hardware and software teams.

The Emulation Engineer will oversee SoC bring-up and debugging, develop automated flows for pre-silicon validation, implement hybrid emulation environments, and create chip-to-chip network models, collaborating with various teams.

As a DFT Intern, you will refine DFT flow automation, support chip-level regression, and aid DFT verification, working closely with design teams.

Lead definition of system-level performance metrics and abstractions across custom silicon, runtimes, compilers, and distributed inference clusters. Design telemetry taxonomies, cross-layer event correlation, time-alignment strategies, and cluster-scale performance reasoning. Build developer tooling and analysis engines to surface actionable insights and influence instrumentation for future hardware.