Jobs at Marvell Technology

Design For Test intern supporting DFT insertion, pattern generation, verification, and testability analysis for complex SoCs. The role includes working with Scan, MBIST, Boundary Scan, and IP macro test flows; resolving DFT issues; automating workflows with Tcl, Python, or shell scripting; improving methodologies and documentation; and presenting project results. Candidates should be pursuing a master’s degree in computer or electrical engineering and understand digital logic and DFT concepts.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K/Teradyne. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows, collaborate with DFx/design, and ensure DFT/MBIST and high-speed interface compliance.

Serves as the primary communications advisor to Marvell’s President and COO. Develops executive speeches, presentations, employee messages, leadership materials, and enterprise communications strategies. Leads communications for strategic initiatives, organizational changes, acquisitions, and integrations while translating complex business, financial, technology, and operational topics into compelling messages. Partners with senior leaders and cross-functional teams, manages sensitive communications, and strengthens executive and internal communications effectiveness.

Owns product strategy, roadmap, lifecycle execution, and business performance for hardware platform solutions supporting AI and cloud data centers. Leads MRD and PRD development, cross-functional alignment, customer engagement, executive presentations, financial modeling, competitive analysis, and go-to-market activities. Requires deep data center networking expertise and experience delivering semiconductor or networking products through production.

Supports semiconductor engineering labs through hardware and software installation, server and networking administration, PCB debugging and precision rework, board bring-up, validation, inventory management, and infrastructure troubleshooting. Performs soldering, BGA and SMT repairs, socket and connector replacement, rack mounting, cabling, diagnostic testing, and documentation. Requires independent work in data center environments, collaboration with hardware and validation teams, and occasional coordination with remote teams.

Leads DFT architecture, implementation, validation, timing analysis, pattern generation, and post-silicon bring-up for complex mixed-signal SoCs. Defines and improves DFT methodologies and tools across multiple chip generations, while mentoring and guiding a team of DFT engineers. Requires deep experience with SCAN, MBIST, IP-DFT, STA, DFX, ASIC design flows, and industry-standard Cadence, Mentor, and Synopsys tools.

Staff DFT Engineer responsible for implementing scan, compression, OCC, wrappers, and MBIST; running ATPG, DFT DRC, simulations, and coverage analysis; supporting timing closure and silicon bring-up; debugging ATE patterns; and automating DFT flows with scripts. The role requires collaboration with physical design and STA teams on advanced ASIC programs.

Define and implement DFT architecture for complex SoCs, including hierarchical DFT, scan, compression, ATPG, MBIST, JTAG, and at-speed testing. Lead DFT sign-off, timing and equivalence checks, silicon debug, failure diagnosis, yield learning, and handoff to physical design and ATE teams. Mentor engineers, coordinate cross-functionally, and improve DFT methodology and automation for advanced-node optical DSP products.

Leads complex semiconductor platform programs from concept through production readiness. Coordinates board, switching, optics, silicon, firmware, software, validation, manufacturing, supply chain, customers, and executive stakeholders. Owns integrated plans, technical integration, risk mitigation, validation, issue resolution, customer commitments, and production transition for hyperscale cloud and networking solutions. Improves program execution practices while balancing schedule, scope, quality, cost, resources, and platform objectives.

Owns technical development programs end to end, including design, cohort planning, training, mentoring, workshops, events, communications, evaluation, and continuous improvement. Partners with engineering teams and senior stakeholders to assess development needs, define objectives and metrics, manage milestones and risks, coordinate global delivery, and apply AI and analytics. Maintains program infrastructure, budgets, vendors, websites, and toolkits while supporting technical conferences and other development initiatives.

Leads the global strategy, governance, roadmap, budget, and delivery of technical training, career development, and technical leadership programs. Partners with senior engineering leaders, conducts skills and workforce analyses, designs scalable programs, and measures outcomes such as retention, productivity, and technical bench strength. Guides regional program managers, mentors team members, evaluates emerging technologies, and aligns technical development initiatives with engineering priorities and product roadmaps.

Assist with designing, testing, debugging, validating, and documenting electrical hardware for optical modules and AI platforms. Use lab equipment to evaluate hardware components, troubleshoot issues, and support verification activities. Maintain schematics, PCB layouts, and bills of materials. Candidates should be enrolled in a related bachelor’s or master’s program, understand electrical engineering and circuit design principles, and be familiar with CAD tools and electrical measurement methods.

Develop and support automated analog and mixed-signal CAD design flows, including parasitic extraction, physical verification, PDK validation, and post-layout processes. Build custom PCells, Pycells, GUI utilities, and automation tools across Cadence, Synopsys, and Siemens environments. Partner with analog designers and EDA vendors to resolve complex flow issues and establish CAD infrastructure for FinFET, BiCMOS, SiGe, and silicon photonics technologies.

Develop scalable embedded network software and SDK components for Marvell Teralynx switching products. Responsibilities include requirements gathering, architecture and design, implementation, unit and functional testing, maintenance, and solving complex technical problems. The role requires embedded switch/router software development using C, C++, and Python, with collaboration across distributed engineering teams.

Leads physical design strategy and RTL-to-GDSII implementation for complex, high-performance SoCs. Oversees synthesis, floorplanning, power grid design, placement and routing, clock tree synthesis, timing closure, signoff, and physical verification. Provides technical direction, scales and mentors physical design teams, manages hiring and performance, drives cross-functional collaboration, and develops advanced methodologies, automation, and design flows for successful tapeouts.

Build and lead Marvell’s sales enablement function from the ground up. Develop sales content, account narratives, battlecards, training, onboarding, launch-readiness programs, and competitive intelligence resources. Partner with Sales, Business Development, Field Applications Engineering, Product Marketing, and Competitive Intelligence teams to improve sales-cycle efficiency and win rates. Establish content governance, self-service enablement, measurement practices, and executive engagement programs for complex semiconductor and AI infrastructure sales.

Leads cross-functional programs to improve semiconductor product gross margins through sourcing cost reduction, yield improvements, cost modeling, and business process changes. Partners with supply chain, finance, engineering, operations, and business units to establish cost targets, assess financial health, conduct cost reviews, identify risks and opportunities, and implement company-wide roadmaps across the product lifecycle.

Supports Marvell’s IT PMO by tracking project status, timelines, budgets, risks, and milestones across active initiatives. Prepares stage-gate governance materials, coordinates reviews, follows up on action items, collaborates with vendors and stakeholders, builds dashboards and status reports, and improves PMO templates, tools, and workflows.

Summer 2027 intern supporting advanced packaging design for photonic fabric products. Responsibilities include developing automated signal and power integrity modeling and simulation flows, applying field solvers, linking package models to simulation decks, and analyzing circuit and packaging designs. The role requires knowledge of electronics, circuit simulation, physical integration, IBIS and S-parameter models, and Python scripting.

Leads board and system design for high-volume semiconductor products from concept through production. Responsibilities include designing high-speed, high-density boards; reviewing schematics and layouts; addressing signal and power integrity; debugging with lab equipment; supporting customers; managing ODM partners; and providing technical leadership throughout development, testing, and production.