Jobs at Marvell Technology

As a Senior Principal Memory Architect, you'll design high-performance memory subsystems and craft the architecture strategy for next-gen cloud and AI products, collaborating with teams to ensure quality and performance.

The Director of Product Engineering will lead the optics product engineering team, manage NPI execution, and drive quality and cost improvements.

Lead the emulation strategy for complex connectivity silicon, define test plans, and enhance validation workflows using advanced emulation platforms. Collaborate across teams to improve productivity and maintain emulation environments.

Lead end-to-end program execution for next-generation optical engines, coordinating cross-functional teams (photonics, analog, packaging, DVT, supply, finance), managing milestones (test, reliability, customer sampling, production ramp), mitigating risks, and reporting to executives to ensure on-time, on-budget, on-spec delivery.

Lead development of ATE test strategy and IP for Advantest 93K, design high‑speed ATE hardware (>112 Gbps), create test plans, convert design test content to production patterns, collaborate with DFx and design teams, and optimize test flows for characterization, wafer sort, and high‑volume manufacturing.

Lead end-to-end program execution for next-generation optical engines and silicon subsystems, coordinating photonics, analog, packaging, supply, DVT, qualification, and finance teams to deliver on-time, on-budget, and on-spec. Manage test, reliability, customer sampling, production ramp, risk mitigation, stakeholder reporting, and executive communication across multiple concurrent workstreams.

Support Storage Business Unit FP&A by building financial models, forecasting, and variance analysis. Drive new product investment planning, month-end accounting controls, project tracking, costing, dashboards, and cross-functional reporting. Partner with business leaders, support planning cycles, and mentor junior team members to deliver actionable financial insights.

Lead substrate procurement strategy including supplier selection, RFQs, negotiations, contracts, capacity planning, cost-reduction roadmaps, supplier performance management, risk mitigation, NPI procurement, and lead a team of commodity managers and buyers.

Architect and develop functional verification environments and reference models. Create verification test plans using constrained-random and directed methods, develop UVM/SystemVerilog/C/C++/DPI testbenches, verify at block/subsystem/SOC levels, debug simulations with EDA tools, and collaborate with logic designers. PCIe and memory subsystem expertise is highly desirable.

Lead the architecture and execution of next-generation data center switch products, collaborating across teams to define features and ensure performance validation.

Design, verify, and deliver memory subsystem IP for custom chips. Develop verification plans and environments, analyze simulation failures, and contribute to coverage-driven verification efforts.

The engineer will design, verify, and evaluate digital circuits in high-speed ICs, improve design methodologies, and collaborate across teams for SerDes IP solutions.

The role involves developing verification plans for high-speed memory interfaces, building verification environments, and collaborating with design teams for compliance and coverage closure in ASIC/SoC projects.

Responsible for defining and implementing IT PMO strategy, managing project portfolios, overseeing program execution, and optimizing financial resources while ensuring stakeholder alignment and compliance with governance frameworks.

Lead worldwide monthly close and consolidations, prepare complex journal entries and reconciliations, assess technical US GAAP accounting (debt/equity), produce financial reporting for executive review, ensure SOX compliance, partner with FP&A/Tax/Treasury/Legal, support external audits, streamline accounting processes, and handle complex ad hoc accounting matters.

Verify circuit designs using cutting-edge technology at Marvell. Responsibilities include developing verification environments, running simulations, and ensuring design meets specifications.

The Inside Sales Representative at Marvell focuses on sales management by developing strategies, managing relationships, analyzing data, and providing actionable insights to achieve revenue goals.

Lead and scale Internal and Executive Communications by establishing operating models, managing complex programs end-to-end, improving processes and tools, supporting executive briefings, partnering cross-functionally, and delivering status, risk, and recommendations to communications leadership.

The Sr. Principal Engineer will lead the development of manufacturing infrastructure for advanced silicon technologies, ensuring seamless transition to high-volume production.

Lead RISC-V MCU/SoC integration and develop bare-metal and RTOS firmware for PHY/SerDes validation. Drive silicon bring-up, HW/SW debug, firmware-driven test automation, validation coverage, and toolchain/debug infrastructure. Collaborate with RTL, validation, and architecture teams to enable reusable, closed-loop validation frameworks across simulation, FPGA, and silicon.