The Product Engineer role involves supporting new product introduction, collaborating across teams, assisting in product characterization, and analyzing production data in a semiconductor environment.

The role involves designing high-speed analog/mixed-signal circuits for optical transceivers, requiring collaboration with multidisciplinary teams and extensive experience in AMS design, specifications, and testing workflows.

The role involves assisting customers with optical subsystem products, optimizing DSP platforms, debugging system issues, and collaborating with cross-functional teams to enhance customer success.

Lead end-to-end DFT implementation and verification for complex SoCs, including MBIST/BISR, boundary scan, IJTAG, ATPG, DFT DRC closure, test coverage improvement, TCL automation, and post-silicon debug working with RTL, Physical Design, and ATE teams.

The Design Verification Engineer will lead complex design verification projects, defining methodologies and ensuring high-quality verification of semiconductor designs across various applications.

As a Design Verification Engineer, you will verify chip designs, develop test plans, and lead teams on verification projects, ensuring high-speed data transfer meets specifications.

Responsible for verifying complex chip designs, leading design verification activities, mentoring engineers, and influencing methodologies across multiple projects.

The Senior Staff Digital ASIC Design Engineer will develop high-performance connectivity silicon and lead the design, integration, and validation of complex ASICs for data centers.

The Senior Staff Digital Design Engineer will lead the design and development of complex ASICs for connectivity solutions, focusing on high-speed datapaths and DSP-driven processing engines in collaboration with architecture and verification teams.

The Senior Executive Compensation Consultant is responsible for overseeing executive compensation governance, planning, regulatory compliance, and analytical support in a public-company environment.

The Director Analyst Relations will shape Marvell's corporate narrative, manage analyst engagements, educate industry analysts, and provide insights to senior leadership.

The role involves leading global engineering applications and labs, managing a multi-year roadmap, modernizing tools, and driving collaboration across teams while ensuring security and compliance.

The role involves physical design and methodology for advanced processor chips. Responsibilities include collaborating with design teams, implementation, mentoring, and scripting for automation.

As an Analog Layout Staff Engineer, you will work with global teams to run simulations and verifications, collaborating closely with designers throughout the project lifecycle, ensuring project specifications are met.

The Principal Engineer will architect simulation test benches, develop and execute test plans, debug failures, and mentor junior engineers in verifying chip designs.

Manage executive travel and global events, including planning and executing events worldwide, vendor management, budgeting, and providing exceptional executive travel experiences.

Design micro-architecture for chips, implement low-power RTL, collaborate on verification and physical design, and support silicon bring-up.

Lead global HR service delivery, establish processes, enhance employee experience through automation and AI, and develop global teams to ensure service excellence.

Lead 2.5D/3D packaging and assembly process development with foundries and OSATs, driving NPI to high-volume manufacturing. Manage qualification, reliability testing, consumable chemistry development, risk mitigation, vendor partnerships, cost reduction, and cross-functional coordination to ensure manufacturability and factory readiness for AI products.

As a Principal Applications Engineer, you will support customers deploying PCIe interconnect technologies, solve system-level issues, and mentor engineering talent.