The RTL/PD Engineer handles RTL-to-PD handoffs, timing closure, floorplanning, and creates automated design flows, collaborating with various teams for seamless integration and quality checks.

Lead the development of a compiler for AI models, optimizing performance and collaborating across teams while mentoring engineers.

The Senior ASIC Design Verification Engineer leads verification planning and execution for AI chip designs, collaborates with cross-functional teams, and innovates verification methodologies.

Lead the design and implementation of runtime systems for an AI accelerator, overseeing architecture, performance tuning, and team mentorship.

The role involves optimizing mid- and backend compiler techniques for custom accelerator hardware, transforming MLIR-based languages, and implementing efficient compilation workflows for AI systems.