SiFive

HQ
Santa Clara
Total Offices: 4
552 Total Employees
Year Founded: 2015
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SiFive Benefits Overview

Compensation + BenefitsCompany CultureWork-Life Balance + Wellbeing

Compensation + Benefits

Offers 401(K)

Offers life insurance

Offers accidental death & dismemberment insurance

Offers disability insurance

Offers supplemental life insurance

Offers company equity

Offers performance bonuses

Offers employee stock purchase plan

Offers employee discounts

Offers dental insurance

Offers health insurance

Offers Health Savings Account (HSA)

Offers Flexible Spending Account (FSA)

Offers vision insurance

Provides family medical leave

Offers generous parental leave

Company Culture

Provides commuter benefits

Provides free snacks and drinks

Utilizes a flexible work schedule

Offers a remote work program

Work-Life Balance + Wellbeing

Offers company-sponsored outings

Offers gym membership

Offers an Employee Assistance Program (EAP)

Offers generous PTO

Provides paid sick days

Offers unpaid extended leave

Provides paid holidays

Provides bereavement leave

Recently posted jobs

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SiFive

Product Power Engineer

5 Days AgoSaved
In-Office
4 Locations
Software
Analyzes and optimizes SiFive IP power consumption across architecture, logic, circuit, RTL, and silicon levels. The role develops power models, correlates them with RTL and silicon results, guides performance-power tradeoffs for high-performance out-of-order CPUs, and improves power analysis workflows. Candidates need advanced computer architecture education, 5+ years of power benchmarking and ASIC optimization experience, and strong problem-solving skills.
Software
Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.
Software
Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.
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