Jobs at SiFive

Develop and maintain the high-performance C++ application for an FPGA-hosted hardware emulation framework. Collaborate with FPGA RTL designers, compiler developers, and RISC-V engineers to enable fast, debuggable, and cost-effective emulation for software and hardware co-design.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

The Director of Sales for Commercial Accounts at SiFive is responsible for prospecting new accounts, creating account plans, managing CRM databases, and improving the sales process while achieving financial targets.

The SOC Architect will lead the development of high-performance SoCs, defining security features, and collaborating with product teams and customers to deliver system IPs.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel). Integrate designs into SiFive's Chisel/FIRRTL framework, enable automatic configuration, verification, and documentation, and collaborate with verification teams and peers to deliver high-performance, configurable interconnect IP.

As a Datacenter System Software Architect at SiFive, you'll design RISC-V Linux systems for datacenters, engage with customers, and optimize performance across software and hardware.

The Executive Business Partner / Assistant will support the CTO and EVP Engineering with executive tasks, business operations, strategic support, and communication, managing complex calendars and travel while driving operational efficiency.

The Strategic Sales Director is responsible for creating account plans, developing customer relations, and achieving sales targets within semiconductor companies. They must possess extensive experience in sales, specifically in IP sales, and be able to communicate effectively with clients.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Lead verification strategy and execution for CPU frontend in high-performance out-of-order cores. Define test plans, checkers, assertions, coverage, and stimulus for branch prediction, instruction fetch, redirects, recovery, and MMU/ITLB interactions. Partner with architects, RTL, performance, and verification teams, apply simulation, formal, and emulation methods, drive block- and core-level signoff, mentor engineers, and build reusable DV infrastructure and methodology.

Lead verification strategy and execution for CPU-subsystem power-management across unit, subsystem, and signoff levels. Define tests, assertions, coverage, and corner-case stress scenarios for DVFS, retention, clock/reset sequencing, power gating, and multi-domain interactions. Drive debug, root-cause analysis, formal and power-aware methods, reusable infrastructure, and mentor engineers to achieve data-center-grade signoff readiness.

Lead verification strategy and execution for advanced hardware prefetch in high-performance out-of-order CPU cores. Define test plans, checkers, assertions, coverage, and stimulus to validate prefetch training, stream management, request generation, DCache interactions, CSR configurability, and corner cases. Collaborate with architects, RTL, performance, and software teams; apply simulation, formal, emulation, and performance validation; drive debug, coverage closure, and mentor engineering teams to raise DV quality and reusable methodology.

Lead verification strategy and execution for a cache-coherent interconnect subsystem, defining plans, assertions, checkers, scoreboards, and coverage. Develop directed and constrained-random scenarios, drive cross-team verification across interfaces and bridges, apply simulation/formal/emulation as appropriate, perform root-cause analysis, and mentor engineers to raise verification quality and reusable infrastructure for high-performance CPU/SoC platforms.

The Verification Architect at SiFive will ensure design fidelity for RISC-V based CPUs, develop verification strategies, and improve quality through collaboration with design teams.

Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.