Jobs at Astera Labs

Responsible for the full lifecycle of verification of complex ASICs, including planning, writing tests, debugging, coverage collection, and working with teams to execute test plans on emulation platforms.

Lead the go-to-market strategy for PCIe signal conditioning products, driving market positioning, execution, and revenue growth while collaborating with cross-functional teams and mentoring staff.

Seeking a Senior Principal Product Manager to lead product roadmap for Astera's connectivity solutions, involving software, firmware, and silicon integration. The role includes engaging with customers, defining strategies, and overseeing cross-functional execution to improve manageability in AI infrastructure.

As a Principal Digital Design Engineer, you'll lead the development of high-speed SerDes transceivers for AI systems, managing design specifications and RTL delivery, collaborating with various teams, and optimizing for performance and power.

The Staff Design Verification Engineer is responsible for the full verification lifecycle, developing tests and collaborating with RTL designers to ensure high-quality ASIC designs for AI connectivity.

Lead and support strategic corporate development initiatives, including acquisitions and partnerships, while collaborating with cross-functional teams to evaluate market opportunities and conduct financial analyses.

The Senior Principal Digital Design Engineer leads digital design architecture for AI connectivity, guiding teams through design execution and cross-functional collaboration while mentoring engineers to ensure high-quality production deliveries.

The Product Cost Manager oversees cost accounting processes, ensuring accurate reporting and insights for decision-making, particularly in the semiconductor sector.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

Lead sourcing strategy for silicon supply chain categories (Foundry, OSAT, Substrates, Test). Develop should-cost and TCO models, negotiate complex agreements, manage supplier relationships and SRM programs, assess supplier financials and IP, and align sourcing with R&D roadmaps to ensure cost savings, risk mitigation, and business continuity for scale-up AI connectivity products.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Design and implement AI-enabled workflows to accelerate silicon development across frontend and backend design. Build generative AI, RAG, and agentic systems integrated with EDA tools, write production Python/C++ pipelines, process design databases/netlists, and develop evaluation frameworks and benchmarks for design quality.

The job involves defining product requirements, engaging with customers, and collaborating with teams to deliver semiconductor products for AI infrastructure.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Responsible for full verification lifecycle of complex ASICs, from planning to debugging coverage measures. Collaborate with design teams and develop test plans.

Build and deploy production AI/LLM systems and agentic workflows for engineering productivity, diagnostics, search, and automation. Design retrieval, tool integration, evals, failure handling, and reusable skills; collaborate with infrastructure and domain teams to monitor and improve systems in production.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

Build and operate ML infrastructure for LLMs and agent systems: model gateways, routing, serving, telemetry, observability, evaluation, cost-aware routing, dashboards, and APIs/SDKs to enable reliable production AI at scale.