Jobs at Astera Labs

Leads functional verification of complex ASICs and SoCs across the full verification lifecycle, including planning, test and sequence development, directed and constrained-random testing, debugging, coverage analysis, and closure. Collaborates with RTL design, software, and system validation teams, executes tests on emulation platforms, automates verification infrastructure, and supports high-quality tape-out for AI infrastructure connectivity products.

Develops microarchitecture and front-end circuit designs for high-performance network controllers, including RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Owns complex ASIC and SoC designs from architecture through GDS and production. Requires expertise in PCIe, UALink, Ethernet, and related protocols, Synopsys or Cadence flows, UVM, small-geometry CMOS, and customer-facing technical leadership.

Leads end-to-end supply chain strategy and execution for PCBA board products, including component and PCB sourcing, contract manufacturing, assembly, testing, inventory, demand planning, and delivery. Manages supplier and contract manufacturer performance, secures constrained components, mitigates capacity and schedule risks, establishes scalable planning processes and metrics, and leads supply chain team members. Partners with engineering, operations, and quality to support reliable delivery in a high-growth AI infrastructure environment.

Architect and develop embedded firmware, host software, drivers, and SDKs for connectivity ASICs and AI infrastructure platforms. Lead hardware-software interface design, cross-functional technical decisions, development processes, code reviews, diagnostics, telemetry, firmware updates, and RAS capabilities. Mentor engineers, influence product architecture and roadmaps, resolve customer system issues, and drive firmware/software solutions across multiple product generations.

Design and implement synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital logic supporting high-speed Ethernet, PCIe, UCIe, UALink, and related protocols. Responsibilities include multi-lane datapaths, encoding, FEC, lane alignment, SerDes interfaces, timing closure, verification support, synthesis, DFT, silicon bring-up, and cross-functional collaboration through tapeout and validation.

Lead firmware verification for SoC and system products, developing white-box and black-box test plans, reviewing code, identifying defects, and validating firmware components and hardware-software interfaces. Create Python-based test automation and manage test environments for PCIe, PHY, security, and other high-speed interfaces. Collaborate with firmware development, system validation, and QA teams to ensure reliable products for data center, server, storage, and networking applications.

Lead RTL implementation of complex digital designs from microarchitecture through silicon sign-off and bring-up. Collaborate with verification, physical design, and DFT teams; support timing closure, clock and reset analysis, formal verification, and ASIC methodology automation. Develop high-speed connectivity designs using SystemVerilog and Python, integrate IP, and contribute to production-quality SoC products involving protocols such as PCIe, Ethernet, or DDR.

Leads the strategy, roadmap, discovery, prioritization, delivery, adoption, and measurement of AI-enabled products and workflows. Partners with business, engineering, IT, security, data, and executive stakeholders to translate needs into scalable solutions. Uses rapid prototyping and AI tools to evaluate concepts, while embedding privacy, security, responsible AI, access controls, and human oversight. Establishes product quality standards, success metrics, change-management practices, and repeatable AI product processes.

Lead end-to-end solution architecture for Oracle Cloud Fusion Financials, including financial modules, integrations, data flows, governance, controls, reporting integrity, and ERP modernization. Partner with Finance, Enterprise Architecture, and implementation teams to support global financial operations, regulatory compliance, implementations, upgrades, and complex system challenges.

Own functional verification for high-speed SerDes and PHY IP. Architect UVM environments, develop SystemVerilog testbenches, define coverage strategies, execute corner-case and protocol verification, and drive coverage closure through tape-out. Validate equalization, clock-data recovery, training, link bring-up, analog handoffs, and mixed-signal models. Collaborate with analog, digital, SoC, firmware, and post-silicon teams while mentoring engineers and guiding verification methodology, reuse, and automation.

Owns RTL synthesis, SDC constraint development, and static timing analysis for high-speed SerDes digital blocks. Drives timing closure from synthesis through sign-off across advanced-node, multi-mode multi-corner designs. Responsibilities include timing optimization, clock and power-domain strategy, ECO guidance, hierarchical analysis, automation, and collaboration with analog, RTL, physical design, verification, and architecture teams.

Develop and own verification strategies for complex connectivity ASICs and SoCs. Build UVM-based SystemVerilog testbenches, create constrained-random and directed tests, define assertions and coverage models, debug simulation failures, automate regressions, close functional and code coverage, and support root-cause analysis and silicon bring-up for PCIe, UALink, and UCI products.

Lead functional verification for advanced ASICs and SoCs, including test planning, SystemVerilog/UVM development, constrained-random testing, debugging, coverage analysis, and coverage closure. Collaborate with RTL designers, software teams, and system validation teams on emulation and hardware-software co-verification. Drive verification methodologies for server and networking applications, including switching architectures, packet processing, PCIe, Ethernet, and NoC designs.

Leads strategic sourcing across semiconductor supply-chain categories including foundries, OSATs, substrates, and test providers. Develops category strategies, analyzes supplier capabilities and costs, builds should-cost and TCO models, negotiates complex agreements, manages supplier relationships, mitigates supply risk, and aligns sourcing decisions with technology roadmaps. Partners with engineering, R&D, and global stakeholders to support product development, capacity, cost savings, supplier performance, and business continuity.

Design, develop, and deploy LLM-powered agentic applications for RTL, physical and analog design, linting, static analysis, and formal verification. Build engineering assistants, dialogue systems, retrieval infrastructure, databases, and dashboards integrated with CAD/EDA workflows. Collaborate with hardware design, design verification, formal verification, and CAD teams to identify challenges and deliver AI-assisted tools. Apply software engineering and AI/ML expertise to accelerate debugging, coverage closure, lint analysis, RTL optimization, and formal proof convergence.

Leads end-to-end engineering programs for analog/mixed-signal semiconductor IP, from specification through tape-out and silicon validation. Coordinates circuit design, layout, verification, systems, product, operations, foundries, and vendors. Owns schedules, milestones, budgets, metrics, risks, stakeholder communication, and program reviews while driving process improvements and resolving cross-functional blockers.

Lead the end-to-end development and technical direction of internal automation platforms. Build full-stack features, backend services, frontend interfaces, databases, access controls, approval workflows, dashboards, and integrations with SaaS, cloud, and identity systems. Automate IT, HR, and Finance workflows involving onboarding, offboarding, asset tracking, entitlements, audit logging, and access reviews. Personally write code, evolve schemas, maintain testing, establish engineering standards, and use AI-assisted development tools.

Architects and develops firmware and microcontroller subsystems for SoC and systems products. Responsibilities include C/C++ firmware and SDK development, Python scripting, HW-SW interface implementation and testing, unit testing, build automation, source control, CI workflows, and collaboration with hardware designers and customers. Preferred work includes RTOS, boot ROM, pre-silicon simulation and emulation, and secure boot technologies.

Leads and develops a US-based technical program management team responsible for advanced ASIC programs from architecture through production release. Oversees milestone planning, dependencies, execution reviews, risk mitigation, budgeting, resource allocation, and readiness for tapeout, power-on, validation, qualification, and manufacturing. Partners with engineering, executives, customers, and external partners while driving consistent reporting, accountability, and cross-functional issue resolution.

Own strategic partnerships with CPU platform providers, ODMs, OEMs, and system integrators. Drive roadmap alignment, interoperability, reference designs, joint business planning, partner agreements, co-marketing, sales enablement, and ecosystem-influenced design wins. Translate AI infrastructure technologies into compelling rack-scale solutions, influence product and go-to-market strategy, present to executives and customers, and represent the company at industry events. The role is based onsite in San Jose five days weekly and requires approximately 25% travel.