Jobs at Astera Labs

Leads functional verification for high-speed SerDes and PHY IP used in AI connectivity products. Responsibilities include architecting UVM environments, developing SystemVerilog testbenches, driving coverage closure, validating physical-layer protocols and link training, supporting analog/mixed-signal co-simulation and RNM, debugging regressions, and mentoring verification engineers. The role collaborates with analog designers, SoC integration, firmware, post-silicon validation, and customer engineering teams.

Design and develop advanced-node CMOS integrated circuit layouts for high-speed analog circuits, including PLLs, DLLs, ADCs, regulators, amplifiers, transmitters, receivers, and CDRs. Responsibilities include floor planning, parasitic and skew reduction, matching, EMIR and antenna compliance, DRC/LVS verification, process yield management, test procedure development, and semiconductor process technology support.

Lead front-end digital design for high-performance PCIe, CXL, UALink, and Ethernet devices from requirements and architecture through RTL, verification, tape-out, and shipment. Manage and mentor 6–8 digital design engineers, establish RTL quality standards and signoff processes, resolve performance, power, area, clocking, and integration issues, and coordinate execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Leads design verification for complex connectivity IPs and SoCs using UVM and SystemVerilog. Defines verification strategies, develops reusable environments, drives coverage closure and sign-off, debugs RTL and protocol issues, and leads verification of CXL, PCIe, Ethernet, and related interfaces. Provides technical leadership, mentors engineers, improves automation and methodologies, and collaborates with architecture, RTL, firmware, validation, emulation, FPGA, and silicon teams.

Own the architecture, micro-architecture, RTL implementation, verification, timing closure, DFT, IP integration, and silicon bring-up of complex digital blocks for advanced AI connectivity SoCs. Collaborate with verification, physical design, firmware, and post-silicon teams to deliver production-quality designs using advanced CMOS nodes. Mentor engineers and improve design methodologies and CAD automation.

Own end-to-end RTL-to-GDS physical design for advanced-node, high-performance SoCs, including synthesis, floorplanning, placement, clock-tree synthesis, routing, timing, power, physical verification, and tapeout signoff. Lead methodology development, ECO closure, and cross-functional integration with RTL, DFT, analog, package, and CAD teams. Mentor engineers and guide technical decisions across complex connectivity silicon programs.

Architect and implement complex digital blocks and subsystems for high-performance semiconductor connectivity products. Responsibilities include micro-architecture, RTL coding, verification collaboration, timing closure, DFT implementation, silicon bring-up, debug, and production delivery. The role owns designs from architecture through GDS, collaborates across verification, physical design, DFT, and firmware teams, mentors engineers, and improves silicon development processes and methodologies.

Designs and implements front-end digital circuits for high-performance networking and switch ASICs, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and silicon bring-up. Owns complex designs from architecture through GDS and production while working with PCIe, UALink, Esun, and Ethernet protocols. Requires expertise with Synopsys or Cadence flows, UVM verification, small-geometry CMOS, and customer-focused technical leadership.

Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through verification, silicon bring-up, characterization, and debug in advanced FinFET processes. Establish design methodologies, collaborate across engineering teams, conduct technical reviews, and mentor analog engineers developing connectivity products for AI infrastructure.

Architect and develop firmware and microcontroller subsystems for SoC and systems products. Build C/C++ firmware and SDKs, boot ROMs, secure boot flows, and hardware-software interfaces. Collaborate with logic designers, conduct pre-silicon simulation and emulation, develop unit tests, and support software build, source-control, code-review, and CI workflows. The role is customer-facing and requires independently prioritizing multiple tasks while supporting complex server, storage, and networking silicon products.

Leads package signal and power integrity architecture, simulation, optimization, and signoff for advanced semiconductor packages and high-speed connectivity products. Responsibilities include SI/PI modeling, SerDes and PCIe/CXL analysis, PDN design, chip-package-board co-design, advanced packaging integration, simulation-to-measurement correlation, routing guidelines, methodology development, vendor coordination, and mentoring. The role requires cross-functional technical leadership through production ramps while balancing performance, cost, manufacturability, reliability, yield, and schedule.

Architects and maintains ASIC and SoC emulation environments for pre-silicon validation. Integrates RTL, transactors, protocol models, software, and test infrastructure for hardware-software co-simulation. Verifies PCIe, Ethernet, memory, storage, and other interfaces; develops reusable models, tests, checkers, and debug methods; analyzes coverage and performance; and leads cross-functional debugging across design, verification, firmware, and systems teams.

Own physical design and signoff for complex connectivity ASICs from RTL through GDS. Drive synthesis, place-and-route, extraction, timing closure, ECOs, EM-IR, Formality, and DRC/LVS across blocks and full chips. Collaborate with RTL, verification, implementation, and top-level teams on constraints, clocking, I/O timing budgets, hierarchical models, and convergence. The role requires advanced-node experience, high-speed SERDES/DDR knowledge, scripting, and proficiency with Cadence or Synopsys toolchains.

Own functional verification of high-speed SerDes and PHY IP for AI connectivity platforms. Architect UVM environments, define coverage and sign-off strategies, develop SystemVerilog testbenches, verify equalization, CDR, training, and link bring-up, and drive coverage closure through tape-out. Collaborate with analog, digital, SoC, firmware, post-silicon, and customer teams on AMS co-simulation, RNM, emulation, and protocol compliance. Mentor junior engineers and lead verification methodology and IP reuse improvements.

Develop and support complex mixed-signal SoC ATE test solutions from design and initial samples through high-volume production. Define test strategies and plans, select tester platforms, develop wafer-sort and final-test hardware and programs, optimize test coverage and time, and lead silicon bring-up, debug, and bench-to-ATE correlation. Collaborate with design and manufacturing partners while testing high-speed SerDes and connectivity protocols.

Leads and grows the ATE Test Engineering organization, defining test strategies for high-speed mixed-signal and SoC products from silicon bring-up through high-volume manufacturing. Oversees wafer-sort and final-test hardware, ATE program development, characterization, debug, coverage, yield, cost, and test-time optimization. Partners with design, DFT, product engineering, operations, and manufacturing teams to deliver production-ready connectivity products and improve quality and execution.

Leads complex analog/mixed-signal semiconductor programs from specification through tape-out and silicon validation. Responsibilities include developing schedules, managing milestones, budgets, dependencies, risks, and deliverables; coordinating circuit design, layout, verification, validation, systems, operations, foundries, and vendors; leading program reviews; communicating status and trade-offs; and improving program management processes.

Lead the go-to-market strategy for fabric switch and memory controller solutions, focusing on product positioning and market intelligence while collaborating with cross-functional teams and mentoring a marketing team.

Partner with R&D business unit leadership to manage annual budgets, quarterly forecasts, and performance analysis. Develop financial models, interpret results versus budget, assess risks, and provide strategic recommendations. Collaborate with Corporate Finance and support business analysis and process improvements.

The Product Quality Engineer will perform failure analysis, drive root-cause identification, collaborate with teams, and utilize lab instrumentation to ensure high-quality AI connectivity solutions.