Jobs at Astera Labs

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Lead RTL design and implementation for complex silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design to achieve timing closure and tapeout. Mentor engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Lead and execute RTL-to-GDS physical implementation for advanced-node connectivity SoCs: floorplan, placement, CTS, routing, timing/power signoff, verification, ECO/tapeout, and mentor engineers while partnering cross-functionally to define methodology and ensure production-quality deliverables.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

The Principal Product Applications Engineer will engage with customers, support PCIe product adoption, troubleshoot system issues, and create technical documentation while collaborating with cross-functional teams.

The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

Lead RTL design and implementation for complex connectivity IP blocks from microarchitecture to synthesis sign-off. Partner with architecture, verification, DFT, and physical design to achieve timing closure and silicon readiness. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and ensure high-quality, PPA-focused deliverables for PCIe/CXL/Ethernet-based SoC integration.

Develop, optimize, and maintain embedded firmware for optical engines and photonic integrated circuits, including control and calibration of optical modules and high-speed link optimization.

Lead customer-facing technical engagements for optical connectivity, driving solution adoption, link bring-up, debug, and system validation. Partner with silicon, firmware, hardware, and optical module partners to develop test methodologies, documentation, and field enablement while mentoring engineers and representing the company at industry forums.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead RTL design and implementation for connectivity silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure, CDC, lint, and low-power goals. Mentor engineers, debug pre- and post-silicon issues, and drive methodology for timely tapeouts.

Lead architecture and hands-on design of high-speed analog/mixed-signal blocks (SerDes, PLLs, ADC/DACs, references). Define specifications, run PVT/Monte Carlo simulations, drive layout and floorplanning, lead silicon bring-up and characterization, and mentor engineers while collaborating with digital, system, product, and packaging teams.

Lead end-to-end program planning and execution for AMS IP development from specification through tape-out and silicon bring-up. Orchestrate cross-functional teams (circuit design, layout, verification, validation), manage schedules, risks, budgets, and vendor/foundry coordination, and drive process improvements and stakeholder alignment to deliver high-quality silicon on schedule.

Lead advanced packaging R&D for photonics products, defining process flows (wafer/panel/die), integrating EIC-to-PIC, qualifying materials and equipment, partnering with OSATs and vendors, and driving yield, reliability, PDKs, and packaging design rules for NPO/CPO products.

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.