Teams at Astera Labs

Lead end-to-end solution architecture for Oracle Cloud Fusion Financials, including financial modules, integrations, data flows, governance, controls, reporting integrity, and ERP modernization. Partner with Finance, Enterprise Architecture, and implementation teams to support global financial operations, regulatory compliance, implementations, upgrades, and complex system challenges.

Own functional verification for high-speed SerDes and PHY IP. Architect UVM environments, develop SystemVerilog testbenches, define coverage strategies, execute corner-case and protocol verification, and drive coverage closure through tape-out. Validate equalization, clock-data recovery, training, link bring-up, analog handoffs, and mixed-signal models. Collaborate with analog, digital, SoC, firmware, and post-silicon teams while mentoring engineers and guiding verification methodology, reuse, and automation.

Owns RTL synthesis, SDC constraint development, and static timing analysis for high-speed SerDes digital blocks. Drives timing closure from synthesis through sign-off across advanced-node, multi-mode multi-corner designs. Responsibilities include timing optimization, clock and power-domain strategy, ECO guidance, hierarchical analysis, automation, and collaboration with analog, RTL, physical design, verification, and architecture teams.