Teams at Astera Labs

Design and architect high-speed analog and mixed-signal circuits (PLLs, LDOs, SerDes, ADC/DAC, references) in advanced FinFET nodes. Lead silicon bring-up, characterization, and validation; define test plans; set analog methodology and best practices; collaborate cross-functionally and mentor junior engineers through full-chip delivery.

Partner with R&D business unit leadership to manage annual budgets, quarterly forecasts, and performance analysis. Develop financial models, interpret results versus budget, assess risks, and provide strategic recommendations. Collaborate with Corporate Finance and support business analysis and process improvements.

Lead the go-to-market strategy for fabric switch and memory controller solutions, focusing on product positioning and market intelligence while collaborating with cross-functional teams and mentoring a marketing team.