Jobs at Blue Origin

Leads end-to-end technical programs for TeraWave’s global ground networking infrastructure, including IP/MPLS backbone deployment, data center and Point of Presence expansion, site selection, facility build-outs, vendor and procurement coordination, and regulatory approvals. Owns software roadmaps, integrated delivery plans, dependencies, risks, and critical paths while aligning software, hardware, systems engineering, integration, and operations teams.

Develop high-performance network edge software for TeraWave satellite communications Points of Presence. Responsibilities include building C/C++ packet-processing applications, optimizing line-rate performance at 100G/400G speeds, implementing routing protocols and tunneling, integrating SmartNIC and FPGA accelerators, and benchmarking dataplane performance. The role requires Linux systems programming, networking fundamentals, and proficiency in Rust, C, or C++.

Design and develop FPGA, digital ASIC, and mixed-signal ASIC solutions using HDL. Lead verification, test-bench development, timing and noise analysis, signoff, physical design, lab integration, and troubleshooting. Collaborate with systems, firmware, architecture, and product engineering teams to resolve implementation challenges. The role also supports full ASIC/FPGA lifecycles and may involve communications systems, DSP, EDA tools, and mentoring junior engineers.

Design and operate AI-powered multi-agent systems for incident triage, root-cause analysis, and self-service debugging. Build knowledge bases, ingestion and retrieval pipelines, AWS infrastructure, evaluation frameworks, guardrails, and operational documentation. Partner with platform, operations, software, and domain teams to convert production incidents into reliable AI tools and deploy them into audited production environments.

Leads physical implementation and top-level integration of RF/mmWave, analog, and mixed-signal ICs. Responsibilities include custom layout, floorplanning, routing, ESD and DFM, physical verification, parasitic optimization, tape-out preparation, and foundry database release. The role provides technical leadership, establishes layout methodologies, mentors engineers, manages schedules and risks, and coordinates internal and external teams developing advanced communication systems.

Leads production test strategy for RF, mmWave, and mixed-signal ASICs. Defines wafer sort and final test strategies, develops ATE tests, establishes packaged RF test approaches, and partners with design, DFT, foundry, manufacturing, and OSAT teams. The role drives test coverage, manufacturability, yield, correlation, throughput, and cost optimization while mentoring test engineers across front-end IC and digital beamformer programs.

Leads architecture, development, integration, verification, and delivery of embedded firmware for custom digital ASICs. Responsibilities span ROM and runtime firmware, hardware/software interfaces, pre-silicon simulation, post-silicon bring-up, system validation, production testing, manufacturing diagnostics, automated testing, and release management. Provides technical leadership, resolves complex integration issues, establishes engineering standards, and mentors engineers across ASIC, hardware, communications, test, and manufacturing teams.

Design digital hardware for the TeraWave satellite communications SOC, owning modem and PHY RTL from system specifications through microarchitecture, integration, synthesis, and timing closure. Responsibilities include signal-processing hardware, Arm compute subsystem logic, AXI and SRAM integration, CoreSight debug infrastructure, GPIO, clock/reset architecture, and collaboration with verification and physical design teams to deliver production silicon.

Owns system-on-chip performance analysis for the TeraWave satellite communications program, covering pre-silicon modeling, emulation-based verification, post-silicon validation, memory bandwidth and latency, Ethernet throughput, and performance budgeting. The role establishes analysis methodology, identifies bottlenecks, validates projections against silicon results, and provides technical leadership across architecture, hardware, firmware, and software teams.

Own DFT architecture and test strategy for large multi-block TeraWave SoCs. Define scan, compression, boundary scan, test access, and BIST specifications; implement DFT infrastructure; generate and validate ATPG vectors; debug ATE pattern failures; support silicon bring-up, defect analysis, yield improvement, and test coverage reviews. Provide technical leadership across design, physical design, verification, and product engineering teams.

Leads RTL design and microarchitecture for TeraWave’s modem system-on-chip. Defines communication-focused architecture, develops Arm compute logic and AXI/SRAM integrations, integrates CoreSight debug, and drives clock, reset, GPIO, memory, Ethernet, and SoC-level integration. Coordinates technical decisions across system, software, performance modeling, and FPGA prototyping teams from specification through production silicon. Supports synthesis, timing constraints, and timing closure.

Own verification planning and execution for complex ASIC and SoC blocks, subsystems, and full-chip systems. Develop simulation, formal, and processor-driven verification environments, including scoreboards, monitors, assertions, coverage, regression infrastructure, and reference models. Drive coverage closure, regression health, and sign-off readiness while applying AI-assisted stimulus generation, triage, and analytics. Mentor junior engineers and help establish verification methodology for a new satellite communications silicon program.

Develop and lead transistor-level analog and mixed-signal IC layouts in advanced FinFET technologies. Responsibilities include floorplanning, device placement, routing, physical verification, parasitic extraction, power distribution, tape-out preparation, and resolving DRC/LVS issues. The role collaborates with circuit designers, CAD engineers, and foundry partners, while leading reviews, documenting best practices, and mentoring junior layout designers.

Deploys and operates machine learning systems for automated manufacturing. Responsibilities include building scalable data and ML infrastructure, automating training and deployment pipelines, monitoring production models, integrating AI with automation and OT systems, optimizing performance, managing incidents, ensuring security and privacy, evaluating ML tools, and mentoring engineers. The role collaborates with data scientists, data engineers, software engineers, and manufacturing automation teams to deliver reliable AI solutions.

Own end-to-end integration and verification for TeraWave RF and optical communications systems, including payloads, terminals, ground stations, and satellite links. Lead architecture, requirements traceability, lab and field testing, HITL emulation, automation, anomaly resolution, and on-orbit validation. Direct cross-functional teams, develop test infrastructure and software, guide technical strategy, manage vendors and roadmaps, and provide technical leadership across complex space communications programs.

Leads end-to-end design of high-frequency phased-array antennas for space communications across X, Ku, and Ka bands. Defines RF architectures, performs EM simulations, collaborates with RFIC, DSP, mechanical, and thermal teams, and oversees fabrication, testing, environmental qualification, and deployment. Mentors engineers and drives technical design reviews and analysis.

Lead verification planning and execution for complex ASIC/SoC digital subsystems. Develop UVM testbenches, reference models, scoreboards, protocol monitors, and assertions. Drive coverage closure, regression health, and verification signoff. Identify corner cases, collaborate across design, systems, DFT, firmware, and physical design, and support emulation, prototyping, and post-silicon debug.

Leads the industrial design of TeraWave’s consumer-facing satellite communications User Terminal, owning form factor, aesthetics, CMF, user-facing components, and design specifications. Develops concepts, renderings, CAD models, prototypes, and production-ready designs while collaborating with mechanical, electrical, RF, product, and supplier teams. Ensures manufacturability, antenna and thermal compatibility, structural integrity, brand alignment, and cosmetic validation through production.

Design and route complex multilayer PCBs for RF, mmWave, digital, mixed-signal, and high-power systems. Perform stackup, signal integrity, impedance, EMI/EMC, and manufacturability analysis; create libraries, DRCs, fabrication and assembly documentation; collaborate with electrical engineers and fabricators; support board bring-up and design for space environments.

Lead advanced analog and mixed-signal IC design in CMOS and SiGe technologies, including filters, amplifiers, data converters, calibration, ESD, clocking, biasing, and power management. Use Spectre and AMS flows, oversee layout and verification, support tape-out, and collaborate on system architecture, validation, product engineering, and silicon characterization. The role also includes mentoring junior engineers and optimizing circuit performance, yield, and reliability for satellite communications systems.