Jobs at Bolt Graphics

Develop and optimize HPC software for computationally intensive workloads across CPU and GPU architectures. Responsibilities include parallel algorithm development, performance profiling, memory and scalability optimization, GPU enablement, compiler and systems-level improvements, and support for scientific applications such as physics, fluid dynamics, and molecular dynamics. The role also contributes to architecture, technical decisions, code reviews, research, feature development, and collaboration across distributed engineering teams.

Lead the architecture, development, and bring-up of embedded firmware for advanced GPUs and digital integrated circuits. Develop boot software and device drivers, manage GPU execution and system control, and support silicon, memory, interconnect, and power subsystems. Collaborate with architecture, RTL, verification, validation, and systems software teams. Lead root-cause analysis, design and code reviews, cross-functional execution, and mentor firmware engineers.

Research and analyze rendering algorithms, translate graphics concepts into computationally efficient models, conduct competitive and performance benchmarking, and collaborate with hardware architects to define proof-of-concept features and system requirements. The role focuses on graphics processors, hardware-based ray tracing, performance modeling, and communicating technical findings to leadership.

Owns ERP platform selection, implementation, configuration, integrations, data governance, reporting, and continuous improvement. Ensures accurate manufacturing, supply chain, inventory, costing, procurement, and financial data across ERP, PLM, MES, and external partners. Leads system administration, release management, user enablement, data quality controls, audits, and cross-functional governance while supporting production scale and financial compliance.

Own the enterprise master data architecture and PLM strategy across engineering, supply chain, finance, and manufacturing. Design item master schemas, governance standards, data-quality controls, and digital-thread integrations. Lead PLM platform selection, implementation, migration, workflow configuration, and PLM-to-ERP connectivity. Establish supply-chain data syndication, BOM audits, and compliance processes. The role requires strong hardware development, EDA, CAD, systems integration, ETL, SQL, and data governance expertise, plus cross-functional technical leadership.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

Develop executable models, simulations, and analytical workflows for SoC and IP systems. Define ASIC requirements, translate system specifications into block- and circuit-level designs, analyze microarchitecture trade-offs across performance, power, and area, and collaborate with product, architecture, and SoC design teams. Improve modeling methodologies, support model-driven design, and correlate pre-silicon models with post-silicon performance.

Lead product definition, system architecture, and lifecycle execution for PCIe accelerator cards and 2U HPC servers. Own hardware requirements, memory and networking strategy, thermal and power trade-offs, silicon-to-system validation, NPI, mass production, ODM/EMS partnerships, BOM optimization, and hardware ecosystem development. The role requires expertise in high-speed PCIe design, DDR5/LPDDR5X or HBM memory, embedded processors, Linux, high-bandwidth networking, and post-tape-out hardware delivery.

Serve as the technical counterpart to the commercial team for HPC and computational engineering customers. Lead workload discovery, performance analysis, benchmarking, proofs of concept, technical evaluations, and deployment planning. Translate customer needs into engineering requirements, explain Bolt’s GPU architecture, resolve technical blockers, develop technical materials, and assess technical fit. Support strategic partners, national laboratories, government organizations, and industry events while bringing customer feedback into product strategy.

Own end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics form factors. Define physical topologies, high-speed interconnects, PCB stack-ups, power delivery, telemetry, and management infrastructure. Lead JDM/ODM engineering partners through layout, bring-up, validation, debug, failure analysis, DFX reviews, and high-volume manufacturing. Collaborate across silicon, signal and power integrity, thermal, and mechanical engineering teams to deliver high-performance graphics hardware.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Conduct research on high-performance computing algorithms, translate advanced mathematics into discrete computational models, benchmark and analyze competing approaches, provide performance estimations, and collaborate with hardware architects to define proof-of-concept features and system requirements.

The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.

Lead the architecture definition for advanced semiconductor products, focusing on SoC design, performance modeling, and cross-functional collaboration in a tech lead role.