Jobs at Bolt Graphics

The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.

Develop and maintain a high-performance host-side driver stack implementing industry-standard graphics and compute APIs (Vulkan, OpenGL, OpenCL, SYCL) on top of a proprietary RISC-V GPU API. Contribute to open-source projects like Mesa, run Khronos CTS conformance tests, participate in standards groups, coordinate with GPU driver team, and build toolchains for development, optimization, and debugging.

Develop and optimize an LLVM-based compiler backend for a RISC-V vector GPU, design optimization passes for parallel vector workloads and intrinsics, build GPU execution and host emulation environments, collaborate with hardware architects and driver teams, and create toolchains for development, optimization, and debugging.

Lead the architecture definition for advanced semiconductor products, focusing on SoC design, performance modeling, and cross-functional collaboration in a tech lead role.

Lead design and implementation of a high-performance host-side driver stack mapping industry-standard graphics and compute APIs (Vulkan, OpenGL, OpenCL, SYCL) onto a proprietary RISC-V GPU API. Contribute to open-source (Mesa), run Khronos conformance tests, participate in standards groups, coordinate with GPU driver team, and build tooling for development, optimization, and debugging.

Lead the development of a high-performance compiler stack for GPU architecture, focusing on optimization passes, collaboration with hardware architects, and team coordination.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

Coordinate customer and partner onboarding, manage executive support and calendars, track sales pipeline and KPIs, maintain BD documentation, coordinate cross-functional projects, organize travel, support recruiting, and build scalable onboarding and enablement processes to grow business development operations.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead enterprise master data architecture and PLM implementation, design item master and lifecycle schemas, build data quality and ETL pipelines, integrate CAD/EDA and PLM with ERP/MES, oversee data governance, BOM audits, and supply-chain data syndication for high-volume semiconductor manufacturing.

Plan and oversee low-level software and driver development for graphics processors. Manage schedules, risks, deliverables, and cross-team coordination; report progress to stakeholders; improve PM processes; coordinate with other PMs; communicate closely with engineers and executives. On-site 3-4 days/week in the Bay Area with occasional travel.

Support cross-functional teams by owning operational workflows, vendor and office logistics, and ad hoc tasks. Coordinate IT, HR, Legal, Finance, Business Development, and Engineering workstreams, track progress, remove blockers, build consensus, and identify process improvements to increase organizational efficiency in a fast-paced startup environment.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

Manage and maintain software configuration processes, repositories, baselines, and audits. Lead configuration control boards, produce compliance reports, train staff, resolve configuration discrepancies, and support cross-team product delivery to ensure software stability and integrity.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Conduct research on high-performance computing algorithms, translate advanced mathematics into discrete computational models, benchmark and analyze competing approaches, provide performance estimations, and collaborate with hardware architects to define proof-of-concept features and system requirements.

Write and develop a ~5-minute 3D animated short and supporting content: brainstorm, outline, script, character briefs, set descriptions, social media sketches, and collaborate with creative leadership and storyboard artists through pre-production to deliver a polished script for animation.