Jobs at Bolt Graphics

Develop executable models, simulations, and analytical workflows for SoC and IP systems. Define ASIC requirements, translate system specifications into block- and circuit-level designs, analyze microarchitecture trade-offs across performance, power, and area, and collaborate with product, architecture, and SoC design teams. Improve modeling methodologies, support model-driven design, and correlate pre-silicon models with post-silicon performance.

The Controller owns accounting operations, financial reporting, monthly and annual close, GAAP compliance, internal controls, audits, tax support, and equity compensation accounting. The role administers QuickBooks and Carta, supervises accounting staff, improves finance systems and processes, supports budgeting and forecasting, and prepares investor and board reporting. The Controller also partners with auditors, tax advisors, legal counsel, and executives while building scalable finance operations for a growing semiconductor startup.

Lead product definition, system architecture, and lifecycle execution for PCIe accelerator cards and 2U HPC servers. Own hardware requirements, memory and networking strategy, thermal and power trade-offs, silicon-to-system validation, NPI, mass production, ODM/EMS partnerships, BOM optimization, and hardware ecosystem development. The role requires expertise in high-speed PCIe design, DDR5/LPDDR5X or HBM memory, embedded processors, Linux, high-bandwidth networking, and post-tape-out hardware delivery.

Serve as the technical counterpart to the commercial team for HPC and computational engineering customers. Lead workload discovery, performance analysis, benchmarking, proofs of concept, technical evaluations, and deployment planning. Translate customer needs into engineering requirements, explain Bolt’s GPU architecture, resolve technical blockers, develop technical materials, and assess technical fit. Support strategic partners, national laboratories, government organizations, and industry events while bringing customer feedback into product strategy.

Own end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics form factors. Define physical topologies, high-speed interconnects, PCB stack-ups, power delivery, telemetry, and management infrastructure. Lead JDM/ODM engineering partners through layout, bring-up, validation, debug, failure analysis, DFX reviews, and high-volume manufacturing. Collaborate across silicon, signal and power integrity, thermal, and mechanical engineering teams to deliver high-performance graphics hardware.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Conduct research on high-performance computing algorithms, translate advanced mathematics into discrete computational models, benchmark and analyze competing approaches, provide performance estimations, and collaborate with hardware architects to define proof-of-concept features and system requirements.

The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.

Develop and maintain a high-performance host-side driver stack implementing industry-standard graphics and compute APIs (Vulkan, OpenGL, OpenCL, SYCL) on top of a proprietary RISC-V GPU API. Contribute to open-source projects like Mesa, run Khronos CTS conformance tests, participate in standards groups, coordinate with GPU driver team, and build toolchains for development, optimization, and debugging.

Lead the architecture definition for advanced semiconductor products, focusing on SoC design, performance modeling, and cross-functional collaboration in a tech lead role.