Bolt Graphics Logo

Bolt Graphics

RTL Design Tech Lead (ASIC/SoC)

Reposted 3 Months Ago
Be an Early Applicant
In-Office
Sunnyvale, CA, USA
250K-350K Annually
Senior level
In-Office
Sunnyvale, CA, USA
250K-350K Annually
Senior level
The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.
The summary above was generated by AI

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

  • Be Fearless: Unmute yourself. Test boundaries and get proven right.
  • Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
  • Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:

We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership, guiding teams from architecture through tapeout.

The ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments. This candidate must be willing to be an individual contributor, while leading others. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.


What you'll do:

  • Own end-to-end RTL design for major subsystems or full-chip blocks
  • Define micro-architecture aligned with PPA (Power, Performance, Area) targets
  • Lead and mentor a team of RTL engineers (junior to senior ICs)
  • Drive design reviews, coding standards, and best practices
  • Collaborate closely with:
    • Design Verification (DV)
    • Physical Design (PD)
    • STA / Timing / DFT teams
  • Ensure high RTL quality via:
    • Lint, CDC, RDC checks
    • Low-power (UPF) compliance
  • Debug complex issues across:
    • RTL simulation
    • Gate-Level Simulation (GLS)
    • Silicon bring-up
  • Work with foundry and backend constraints (timing, congestion, IR, etc.)
  • Drive schedule, risk mitigation, and execution toward tapeout

Required Qualifications:

  • Bachelor’s or Master’s in Electrical / Computer Engineering
  • 10+ years of experience in ASIC/SoC RTL design
  • Expert-level proficiency in:
    • SystemVerilog / Verilog RTL coding
    • Micro-architecture design
  • Strong understanding of:
    • Timing (setup/hold, STA correlation)
    • CDC/RDC methodologies
    • Reset strategies and clocking architectures
    • Low-power design (UPF/CPF)
  • Proven experience leading blocks through multiple tapeouts
  • Hands-on experience with synthesis (e.g., Design Compiler)
  • Strong debugging and problem-solving ability
  • Excellent communication across cross-functional teams
  • Ownership and accountability for silicon success
  • Ability to operate under tight tapeout schedules

Preferred Qualifications:

  • Experience in advanced nodes (e.g., 12FFC, 7nm, 5nm)
  • Strong GLS expertise (SDF, X-propagation, power-aware sims)
  • Knowledge of DFT (scan, MBIST, compression)
  • Experience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems
  • Scripting proficiency (Python / Tcl)
  • Prior collaboration with foundries such as TSMC
  • Experience in startup environments or first-silicon efforts
  • Exposure to packaging (flip-chip, bump planning, IO constraints)
  • Experience with low-frequency testchips or rapid prototyping
  • Government clearance is preferred

Leadership Expectations:

  • As an IC, you will provide technical direction and architectural clarity
  • Mentor and grow team members
  • Drive high engineering standards and design quality
  • Influence cross-functional decisions
  • Balance hands-on work with leadership responsibilities

Compensation Range: $250,000–$350,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.

Benefits:

  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match
  • WFH Hardware


Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

HQ

Bolt Graphics Sunnyvale, California, USA Office

440 N Wolfe Rd, Sunnyvale, CA , United States, 94085

Similar Jobs

19 Minutes Ago
Hybrid
Senior level
Senior level
Consumer Web • eCommerce • Information Technology • Retail • Software • Analytics • App development
Drives sales growth for Lowe’s largest regional professional customers through strategic account management, consultative selling, market research, customer visits, jobsite meetings, trade shows, pricing negotiations, and proactive follow-up. Develops account strategies, identifies product opportunities, coordinates with store and district teams, supports customer purchasing processes, and reports sales performance. Builds relationships with senior purchasing decision-makers and manages complex B2B accounts as an individual contributor.
Top Skills: Crm Technology
An Hour Ago
In-Office
151K-205K Annually
Expert/Leader
151K-205K Annually
Expert/Leader
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Leads 18 engineers developing avionics and flight-controls subsystem requirements, hardware/software requirements, supplier technical management, system design, testing, qualification, and flight-test support. Manages staffing, budgets, metrics, schedules, quality, process improvement, and team development while coordinating with senior leadership, suppliers, and cross-functional stakeholders in an Agile environment.
Top Skills: AgileAvionicsEarned Value Management (Evm)Flight ControlsHardware/Software Requirements
An Hour Ago
In-Office
77K-139K Annually
Mid level
77K-139K Annually
Mid level
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Manage personnel security for classified DoD space programs: maintain security records and logs; process clearances, PARs, VARs; use DISS/JADE for risk assessments; support indoctrinations, briefings, self-inspections, and SAP/SCI facility procedures. Ensure compliance with DoD/ICD policies and coordinate with government representatives.
Top Skills: Defense Information Security System (Diss)Joint Access Database (Jade)ExcelMicrosoft PowerpointMicrosoft WordSapnpSci

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account