Teams at Broadcom

Lead end-to-end mainframe DevOps architecture for enterprise customers: design blueprints, run design workshops, set standards, mentor consultants, drive migrations to Endevor/Zowe-based CI/CD integrations, support pre-sales scoping, and serve as primary technical escalation while traveling to client sites.

Design and execute block- and chip-level verification for high-speed interconnect ASICs. Build SystemVerilog UVM testbenches, validate IEEE Ethernet protocols, understand chip architecture, and create scripts/tools to improve verification efficiency. Collaborate with architecture, firmware, physical and layout teams throughout product development.

Design and verify front-end RTL blocks for ASIC cores: define architecture, implement logic, perform synthesis, constraints, simulation and formal verification, analyze timing from physical implementation, debug Verilog designs, and collaborate across global teams within the full ASIC implementation flow.