Teams at Broadcom

Lead block- and top-level ASIC physical design from floorplanning through GDSII stream-out. Execute placement, clock-tree synthesis, routing, timing and power closure, signal-integrity optimization, and IR-drop/electromigration signoff on advanced 5nm, 3nm, and 2nm nodes. Automate design flows using TCL, Python, and Unix shell scripting while providing technical leadership across complex AI and PCIe switch ASIC projects.

Provides hardware design support, technical guidance, board-level debugging, and laboratory validation for semiconductor solutions. Responsibilities include schematic and PCB layout reviews, component selection, board bring-up, functional testing, troubleshooting with lab equipment, board rework, electrical characterization, and creation of customer-facing technical documentation. The role collaborates with cross-functional engineering teams and supports enterprise, frontier lab, and hyperscaler customers.

Manage 20+ concurrent package and PCB design projects for high-performance ASICs, coordinating scope, schedules, resources, engineering teams, customers, and vendors. Develop signal and power integrity methodologies, support package and PCB technologies, communicate project status and risks, and contribute to SI/PI simulations, automation, lab measurements, and design-flow improvements. The role requires on-site collaboration five days per week.