Jobs at Cisco

Provide high-level administrative support to the EVP of Legal, including calendar and meeting management, travel and expense coordination, event and speaking engagement preparation, confidential correspondence, special-project analysis, and mentoring other administrative staff.

Lead global physical design and CAD methodology for advanced ASIC/SoC projects. Define RTL-to-GDSII flows, EDA tool strategy, vendor partnerships, scripting automation, and multi-die/2.5D/3D methodologies while managing and growing a high-performing CAD team.

Provide electrical product engineering for new and sustaining data center networking products from NPI to end-of-life. Responsibilities include DFM, BOM risk management, cost avoidance and reduction, design and manufacturing FMEA, board bring-up and debug, component qualification, yield improvement, cross-functional collaboration with hardware, mechanical, test, process and reliability teams, and running lab experiments/DOE to resolve complex issues.

Serve as the technical interface between customers and internal teams to translate requirements into ASIC and software solutions. Influence product strategy, represent the Silicon One portfolio, collaborate with ASIC, SDK, and software teams, and ensure data-path networking functions meet customer needs.

Develop, integrate, debug, and test Cisco Silicon One software and datapath applications. Collaborate with hardware, systems, partners, and customers on networking protocols, system integration, and diagnostics; add features, tests, and documentation to support product quality and customer deployment.

Lead customer-facing software development for Silicon One NPU products. Define requirements, design and deliver control- and data-plane software using modern C++ and Python, debug with GDB/PDB, mentor engineers, and collaborate with architecture and hardware teams to enable scalable, low-latency networking solutions and drive product adoption.

Serve as a technical interface between customers and internal teams to capture requirements, communicate ASIC and software capabilities, and influence product and ASIC/software roadmaps. Collaborate with ASIC development, SDK, project management, and marketing to drive implementation of data-path functions (routing/switching) and deliver networking solutions that meet customer needs and industry standards.

Lead and mentor a North America software engineering team working on Cisco Silicon One software. Collaborate with internal hardware/software teams, external vendors, and customers to develop, debug, integrate, and test networking datapath applications. Drive SW/HW system integration, add software enhancements, expand testing and debugging capabilities, and provide customer guidance and documentation to deliver next-generation infrastructure products.

Develop and validate block- and full-chip SDC timing constraints, perform STA using industry tools, collaborate with front-end/back-end and DFT teams to close timing, contribute to clocking design and RTL/IP integration, and improve SDC methodologies and verification processes throughout the design cycle.

Design and own front-end ASIC subsystems from microarchitecture and RTL through tape-out. Implement high-frequency RTL in Verilog/SystemVerilog, collaborate with verification and physical design teams to meet timing, power, and area targets, drive debug and post-silicon validation, mentor engineers, and influence system architecture and design processes.

Lead technical design and implementation of a cloud-based Data Center Infrastructure Management product. Build scalable microservices and distributed systems using Java/Go/C++/Python on AWS/GCP/Azure. Collaborate with cross-functional teams to deliver production-ready, maintainable solutions for AI and edge datacenter infrastructure. Hybrid role based in Milpitas, CA.

Lead a customer-focused quality engineering team for strategic Cisco accounts, driving executive reviews, deep root cause analysis, data-driven quality trends, cross-functional corrective actions, field mitigations, and team development to ensure sustained product performance.

Lead full-chip physical design and floorplanning for advanced-node ASICs. Drive RTL-to-GDSII implementation including partitioning, pin assignment, clock/bump planning, P&R, STA, power grid and integrity, physical verification, and signoff. Collaborate with system, package, foundry and IP vendors; improve EDA flows and mentor teams. Apply UPF low-power methodologies and leverage Python/AI tools for productivity.

Lead Spitfire NPI, Common BIOS, and Cygnus Applications teams to deliver Silicon One-based routing platforms. Manage engineering processes, infrastructure, and developer experience; drive AI-powered automation and CI/CD; mentor engineers; enforce quality, security, and performance; and deliver multi-team projects that advance Cisco's platform strategy.

Design and validate complex hardware systems for networking/server products. Drive technology roadmaps, create specifications, collaborate cross-functionally, and perform lab-based hardware validation using oscilloscopes, logic and spectrum analyzers. Participate in FPGA development, board design, and product delivery to production.

Lead end-to-end AI research programs: design experiments, build and evaluate models (including LLMs), synthesize insights, collaborate with product and engineering, mentor colleagues, and communicate results via presentations, papers, and patents to influence enterprise AI product decisions.

Serve as Cisco's domain authority for memory technologies: select, validate, and qualify DRAM/advanced memory for products. Collaborate with design, manufacturing, quality, and vendors to improve memory RAS, lead failure analysis and corrective actions, and influence vendor roadmaps and component choices for next-generation platforms.

Develop and validate block-level and full-chip SDC timing constraints and perform STA to identify and resolve timing issues. Collaborate with front-end and back-end teams on clocking, timing exceptions, and physical design closure. Optionally perform RTL design or IP integration and contribute to full-chip clocking documentation and SDC methodology to ensure correctness early in the design cycle.

Lead qualification of optical devices and assembly processes for WLM and optical transceiver products. Assess suppliers and technologies, perform design/process reviews and reliability risk assessments, develop and execute qualification plans, drive failure analysis and corrective actions, and manage supplier quality across product lifecycle.

Lead architecture and design of backend AI platform services for AI Canvas and related products. Design orchestration, skill execution, intelligent routing, and asynchronous pipelines; integrate LLM platforms; improve observability and reliability at multi‑million MAU scale. Mentor engineers, drive technical decisions, and guide production deployment of LLM-powered features.