Teams at Cornelis Networks

Lead and grow the RTL design engineering team responsible for next-generation networking ASICs. Own RTL delivery schedules, coordinate design verification, emulation, and physical design dependencies, manage timing-closure and tape-out readiness, identify schedule risks, and allocate resources. Develop headcount and organizational plans, lead hiring, and scale globally distributed engineering practices while contributing hands-on expertise in microarchitecture, RTL design, synthesis, verification, and PPA optimization.

Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Collaborate on verification, timing constraints, physical design, post-silicon validation, system debugging, performance optimization, and power-aware Host Fabric Interface designs. The role focuses on Ethernet, networking protocols, high-performance computing, AI interconnects, and SoC development.

Leads verification closure for ASIC modules, subsystems, and SoCs used in AI and HPC networking. Defines verification strategies, develops UVM testbenches, executes functional tests, manages regression and coverage closure, debugs RTL issues, and collaborates with design, software, emulation, hardware, and post-silicon teams. Provides technical leadership, mentoring, coding guidance, and promotes AI tools for verification productivity.