Teams at Credo

Protect company systems, infrastructure, cloud environments, applications, endpoints, and data by investigating incidents, administering security platforms, assessing vulnerabilities, coordinating remediation, conducting security reviews, and improving controls. The role supports monitoring across endpoint, identity, email, network, cloud, and application environments while documenting findings, runbooks, audit evidence, and risk assessments aligned with ISO 27001, NIST CSF, CIS Controls, and MITRE ATT&CK.

Design and implement synthesizable RTL for high-speed SerDes PHY DSP blocks, including equalization and clock-data recovery functions. Define microarchitecture, translate DSP algorithms into RTL, optimize for power, performance, area, and latency, and verify designs. Support ASIC implementation, timing closure, CDC/RDC, DFT integration, silicon bring-up, PHY integration, and system-level debugging.

Designs and verifies complex digital ASIC logic blocks from microarchitecture through tape-out. Responsibilities include RTL design, IP integration, functional and gate-level verification, testbench development, synthesis, timing analysis, lint, CDC, ECO support, and collaboration with physical design, DFT, software, firmware, and systems teams. The role also supports chip bring-up, feature validation, debugging, and successful product delivery.