Teams at Delos Data

Define and guide architecture for high-performance ASICs supporting AI accelerators, networking, and data center workloads. Develop architectural and micro-architectural specifications, model performance, optimize power, performance, and area, and lead trade-off studies and design reviews. Collaborate with RTL, verification, physical design, firmware, and software teams while defining power-management strategies and mentoring engineers.

Design and implement production-ready RTL for complex digital subsystems, translating architectural specifications into scalable microarchitectures. Collaborate with architecture, verification, and physical design teams on correctness, synthesis, timing, power, and area closure. Perform linting, CDC analysis, simulation, debug, integration, and design reviews. Contribute to reusable RTL, design methodologies, tooling, and AI-assisted workflows.

Develop and maintain RTL verification environments for ASIC and FPGA designs using UVM and SystemVerilog. Create coverage-driven plans, directed and constrained-random tests, assertions, and reusable verification components. Analyze simulations, debug design issues, track functional and code coverage, automate regressions with Python, and drive verification through closure. Collaborate with RTL engineers on reviews, testability, and reliable silicon delivery while verifying protocols including AXI, APB, PCIe, Ethernet, SPI, and I²C.