Jobs at Intel

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Lead the design and validation of analog circuits for high-speed SerDes applications, mentoring junior engineers and collaborating with cross-functional teams.

Lead and manage complex engineering programs tied to product and manufacturing systems. Troubleshoot technical roadblocks, align cross-functional teams, scope requirements, prioritize deliverables, run executive reviews, mentor PM teams, and drive process innovation to meet customer and business objectives.

Measure, analyze, and debug power and performance of OEM notebook SoC/CPU platforms rail-by-rail. Set up and calibrate instrumented systems, run benchmarks and competitive analysis, tune workload behavior, and communicate findings to engineering, OEMs, and marketing to support product launches.

Design, implement, and optimize Intel's neuromorphic AI compiler and runtime. Build tooling for performance analysis, verification, debugging, and optimization. Integrate the software stack with robotics and edge AI ecosystems. Collaborate with hardware, compiler, and systems teams and external customers to deliver production-grade, high-performance software.

Measure, analyze, and debug power and performance of Intel and competitor SoC/CPU platforms on Linux and Android/Chromebook. Create rail-by-rail power measurements, develop projections/estimates for unlaunched products, bring up test platforms, align with internal teams, and influence OEMs and marketing for product launches.

Design and implement mixed-signal IP logic: RTL coding, simulation, and optimization to meet power, performance, area, and timing goals. Collaborate with analog, digital, and physical teams, review and fix RTL verification issues, and support SoC customers for high-quality IP integration.

Design, develop, and maintain automated wafer-level test systems and test software for silicon photonics devices. Implement test algorithms, collaborate with device designers and data teams, create procedures and documentation, train technicians, and troubleshoot to improve system performance, reliability, and throughput in production environments.

Drive end-to-end LLM inference performance on Intel GPUs: profile bottlenecks, write and optimize custom GPU kernels (attention, MoE, quantization, fusions), upstream improvements to vLLM/SGLang/PyTorch, and collaborate with architecture and compiler teams to shape hardware roadmaps.

Design, simulate, and optimize silicon photonic components (modulators, passive devices, detectors); perform tolerance and statistical analysis; lead test-chip design, layout, tapeout, testing and validation; develop modeling and test methodologies; analyze test data to close performance gaps; research next-generation photonic architectures; collaborate with cross-disciplinary teams to meet system-level requirements.

The Physical Verification Engineer supports layout verification and parasitic extraction for Intel, ensuring successful design implementations and quality improvements. Responsibilities include technical content development, customer support, and leading verification methodology optimization for CMOS processes.

Lead centralized IT business operations supporting global IT segments: own Plan of Record, drive financial planning and reporting, enable data-driven decisions, improve operational processes, lead cross-functional initiatives, deliver cost efficiencies, and build a high-performing team while partnering with Finance, HR, Legal, and executive stakeholders.

Lead product strategy and roadmap for Ethernet networking products across cloud, enterprise, and service provider markets. Gather and prioritize customer requirements, drive market and competitive analysis, build business cases and pricing, partner with engineering, sales, and marketing for go-to-market, and engage strategic customers and industry forums to influence product lifecycle and adoption.

Characterize semiconductor device behavior and develop/update compact device models for new technologies. Validate and ensure accurate, robust model simulations, support design enablement, and collaborate with process and design teams using scripting and simulation tools.

Drive Intel revenue by building executive relationships, winning design-ins, and co-engineering products to production. Define and execute account-level sales strategies, negotiate complex agreements, manage account plans, and identify opportunities across cloud, AI, connectivity, edge, and data center solutions while collaborating with OEMs, ISVs, and internal teams to meet revenue and KPI targets.

Develop and validate compact transistor models (FinFET, GAA) and simulation methodologies for PDKs. Collaborate cross-functionally to ensure modeling readiness, perform statistical, RF and EM simulations, automate analysis with Python, and integrate innovative techniques like OMI and ML to meet delivery milestones.

Lead physical design timing efforts for next-generation SoCs: perform timing analysis and optimization, generate and validate timing constraints, define PVT conditions, develop timing models and flows, collaborate with clocking, architecture, and logic teams to ensure high-performance, low-power chip integration.

Develop and execute verification plans and testbenches for interconnect and chassis IP; build reusable verification components, constrained-random tests, and debug infrastructure; perform simulation and formal verification, analyze failures, close bugs, plan functional coverage, and improve verification automation and regression quality.

Define and own pod-level reliability specs for compute, memory, storage, network, power, and cooling. Translate SLAs to subsystem requirements, lead FMEA/root-cause analysis and fleet failure analytics, architect RAS features, partner on power/cooling redundancy, and establish HALT/HASS, burn-in, qualification processes while tracking field returns and KPIs.

Perform physical design for neuromorphic chips including floorplanning, partitioning, macro/pin placement, P&R, timing closure, EM/IR/DRC fixes, back-annotated simulation, power/performance optimization, and scripting/tool-flow development.