Jobs at Intel

Lead cross-functional, matrixed teams through the planning, development, validation, implementation, and release of semiconductor Process Design Kits. Manage program objectives, schedules, dependencies, resources, budgets, risks, quality, and stakeholder communication from requirements through deployment. Coordinate engineering, business, foundry, OSAT, EDA vendor, and design enablement partners while supporting advanced memory technology and silicon product development.

Manages software product and engineering activities from definition and planning through execution, production, maintenance, and end of life. Coordinates architects and cross-functional engineering teams, evaluates requirements, validates product definitions, resolves technical gaps, develops product strategies, identifies opportunities, and aligns milestones with business goals. Serves as a central liaison among development, testing, quality, sales, marketing, customers, and executives while overseeing large-scale technical programs.

Designs, develops, tests, and deploys cloud-native applications, microservices, APIs, and backend services on Azure. Ensures cloud security best practices, troubleshoots production issues, and creates manual and automated testing plans. The role requires experience with Azure services, databases, containers, web services, and modern development technologies, with responsibility for building solutions under stringent customer controls.

Support physical verification for Intel leading-edge PDKs by running DRC, LVS, ERC, density, and related checks; investigating violations; debugging runsets and flows; identifying root causes; and implementing solutions. The role also maintains training and user documentation, supports customers directly, clarifies requirements, and collaborates with internal design technology stakeholders to resolve issues and enable customer success.

Develop and debug hardware verification testbenches, constrained-random tests, functional checkers, simulations, and coverage plans for interconnect and chassis IP. Analyze failures, root-cause issues, support regression triage, participate in design and specification reviews, and use AI-assisted coding, scripting, and automation tools. The role provides entry-level training across hardware design, verification methodology, and chip development flows.

Lead end-to-end architecture for modular, scalable SoCs supporting datacenter and agentic computing. Define hardware, firmware, functional specifications, microarchitectures, registers, and performance goals; integrate IP blocks; develop validation infrastructure; analyze benchmarks; and optimize power, timing, performance, and area. Collaborate across architecture, design, systems, and verification teams, influence technology roadmaps, provide technical leadership, and mentor other engineers.

Develops strategic partnerships and enterprise opportunities for Intel-based Physical AI and robotics solutions. Builds adoption strategies, business cases, go-to-market plans, account plans, and co-sell motions with cloud providers, systems integrators, software partners, robot OEMs, and AI model providers. Positions Intel technologies, represents market needs internally, influences product roadmaps, and drives ecosystem-led deployment scale across industries.

Designs and deploys end-to-end Physical AI and robotics solutions across data collection, simulation, model training, optimization, robotic hardware deployment, and fleet operations. Advises enterprise customers, cloud providers, systems integrators, and ecosystem partners on integrating AI workloads with IT, OT, edge, and cloud environments. Leads proofs of concept, technical evaluations, benchmarking, and solution validation while influencing Intel product roadmaps, strategy, and customer adoption.

Lead front-end silicon design and verification for neuromorphic chiplets, IP, processors, and AI accelerators. Translate architectures into microarchitectures, manage design through post-silicon validation, integrate high-speed interfaces and external IP, collaborate on physical design and custom memories, enable pre-silicon software development, and mentor multidisciplinary engineering teams. The role requires ownership of product tape-outs and experience with advanced ASIC methodologies.

Two-year full-time rotational program developing sales, marketing, technical sales, and business skills through three eight-month rotations. Participants support sales strategies, marketing campaigns, customer engagement, business operations, and communications initiatives while building product, technology, customer, analytical, leadership, and communication expertise.

Two-year, three-rotation program developing technical sales and marketing talent. Participants rotate through sales engineering, technical marketing, solution architecture, and related roles while building expertise in Intel products, technologies, customers, sales channels, and industry ecosystems. Responsibilities include developing technical solutions, influencing customer adoption, delivering quarterly objectives, and strengthening leadership, communication, and customer skills through mentoring and customized training.

Drives enterprise sales of Intel-based products and solutions by building relationships with senior business and technical leaders. Leads account planning, upselling, cross-selling, tenders, forecasting, and strategic customer initiatives. Advocates Intel architecture across on-premise, hybrid, and public cloud environments, collaborates with partners and internal teams, gathers customer feedback, and supports joint marketing efforts to increase revenue and customer satisfaction.

Installs, maintains, and supports semiconductor design and compute environments, including EDA tools, automation scripts, design flows, licenses, PDKs, and compute capacity. Resolves tool and methodology issues through tapeout, supports design ramp-up with training and documentation, collaborates with EDA providers and engineering teams, and integrates new tools and methods into scalable workflows.

Installs, maintains, and supports semiconductor design environments, EDA tools, Intel PDKs, licenses, automation scripts, design flows, and compute infrastructure. Resolves methodology and tool issues through tapeout, supports design ramp-up with training and documentation, coordinates with EDA providers and internal design teams, provisions compute capacity, and integrates new tools and methods into scalable workflows.

Perform SoC-level static timing analysis, timing constraint development, timing closure, clock network optimization, and PVT analysis for advanced semiconductor designs. Collaborate with architecture, logic design, clocking, DFT, and physical design teams to resolve timing violations, optimize performance and power, develop timing models, and improve design methodologies, tools, and flows. The role also requires technical leadership, cross-functional communication, mentorship, and ownership of complex engineering challenges.

Leads post-silicon characterization, certification, and technology-readiness activities for SRAM, Register File, and fuse arrays. Develops Vccmin/Vmax predictive models, analyzes large semiconductor datasets, evaluates silicon-to-simulation correlation, assesses risks, and improves certification methodologies. Collaborates cross-functionally with design, device, process, test, yield, and reliability teams to resolve technical challenges and support PDK releases and product deployment. Presents findings to leadership and provides technical mentorship.

Develop and maintain Intel’s asynchronous EDA design automation flow for neuromorphic silicon. Build algorithms, tools, utilities, scripts, and regression tests supporting RTL, verification, physical design, simulation, FPGA emulation, synthesis, and implementation. Create scalable frameworks for early software development and optimize custom low-power, high-performance designs. The role requires full ASIC lifecycle knowledge, multiple tape-outs, strong scripting skills, and experience using AI-assisted engineering tools.

Design and optimize analog and mixed-signal circuits and foundational IP, including ADCs, DACs, voltage regulators, and high-speed I/O. Responsibilities include circuit simulation, floorplanning, verification, tape-out, test planning, post-silicon debugging, and collaboration with architecture, layout, process technology, IP, and product teams.

Lead DFT/DFX strategy for Intel’s neuromorphic silicon program, architecting SoC-level test solutions across synchronous and asynchronous designs. Develop scan insertion, compression, ATPG, test-vector, emulation, and validation flows; collaborate on DFT, DFD, and DFM features for high-volume manufacturing. Lead silicon power-on, tester-content enablement, failure debugging, and reliability improvements while maintaining development tools and flows.

Architect and lead software development tools for Network-on-Chip and SoC development, including debuggers, analyzers, SDKs, IDEs, and related methodologies. Provide technical direction, evaluate requirements, model architectures, review code, solve complex engineering challenges, and collaborate with cross-functional teams and industry technologists. Ensure software quality through debugging, development, validation, performance modeling, and correlation.