Jobs at Intel

Develop and manage device collateral including test chip and scribe line designs, establish and enforce design rules and waivers, collaborate with process and yield teams, analyze parametric data, and optimize monitoring structures for high-volume CMOS manufacturing.

Develop and execute verification plans and testbenches for interconnect and chassis IP; build reusable verification components, constrained-random tests, and debug infrastructure; perform simulation and formal verification, analyze failures, close bugs, plan functional coverage, and improve verification automation and regression quality.

Develop and execute mixed-signal IP verification plans, build UVM/OVM testbenches, perform analog behavioral modeling, debug presilicon issues, analyze coverage, and collaborate cross-functionally to meet design, power, and performance targets.

As a Compiler Engineer at Intel, you will design, develop, and maintain their LLVM-based compiler stack, collaborate with hardware teams, and enhance performance through optimizations and debugging.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

Design and integrate SoC logic: develop RTL (SystemVerilog), collaborate on microarchitecture, integrate/validate IPs, optimize for power/performance/timing, support verification and pre-silicon validation, and ensure secure development and production readiness.

The role involves developing cloud-native applications, defining cloud architecture, building data engineering pipelines, and ensuring security practices across AI/ML solutions and big data integrations.

Manage the product line for Computers for Agents, including defining specifications, driving cross-functional alignment, and presenting strategies to leadership.

Develops RTL logic design and simulation for mixed signal IPs. Participates in architecture definition and optimizes designs for performance goals. Ensures correctness of features through verification processes and supports SoC integration.

The engineer drives technology development for manufacturing, leads sophisticated process design, recommends equipment modifications, and partners with suppliers.

This role involves owning the architecture and design of complex SoC subsystems, leading cross-functional collaboration, ensuring design quality, and mentoring senior engineers.

Design and validate mixed-signal SoC and FPGA control electronics for qubit systems. Architect control signal chains, perform signal integrity and EM modeling, collaborate with qubit and software teams, and prototype, tape-out, and test RF/analog components to scale qubit control.

Design and implement IP logic and RTL (SystemVerilog/Verilog), optimize for power/performance/area/timing, apply low-power techniques (UPF, clock/power gating), debug RTL/CDC issues, define microarchitecture features, and support SoC integration and verification with cross-functional teams.

Develop UVM testbenches and constrained-random/directed tests for mixed‑signal IP. Define verification plans and coverage, run RTL and gate‑level verification, debug failures, analyze coverage, and collaborate with design teams to review specs and improve verification methodology. Support mixed‑signal verification using Verilog analog models.

Design and optimize analog and mixed-signal circuits (power delivery, IPs) for advanced CMOS nodes. Perform circuit simulation, floor-planning, post-layout extraction, verification, and validation. Collaborate with architecture, layout, and validation teams, analyze test data, and iterate designs to meet power, performance, area, timing, yield, and robustness goals.

Designs, develops, and tests software tools for hardware design and manufacturing. Responsibilities include user requirement capturing, coding, automating deployment, and testing software tools.

Lead the design and validation of analog circuits for high-speed SerDes applications, mentoring junior engineers and collaborating with cross-functional teams.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

The CEG Technical Assistant/Chief of Staff supports CEG's strategic initiatives, managing executive operations, stakeholder relationships, and driving business objectives. Responsibilities include collaboration across Intel, facilitating communication amongst teams, and enhancing organizational processes.

Designs and oversees development of Intel GPU AI software across the entire stack, ensuring performance, stability, and ease of use, while mentoring technical leaders and aligning technical strategies with organizational goals.