Teams at MatX

Lead integrated NPI lifecycle for rack- and board-level AI systems, coordinating CM/JDM partners, PLM/BOM/ECO control, factory test deployment, quality and yield metrics, and high-volume ramp readiness while reporting risks and readiness to executives.

Develop and sign-off performant silicon from RTL to GDSII across blocks, subsystems, and full-chip. Lead partitioning, floorplanning, synthesis, P&R, clocking, verification, timing/power sign-off, and collaborate with Design, Verification, and DFT teams to meet tapeout milestones.

Design and implement compilers for proprietary hardware architecture, focusing on midend and backend development, while providing hardware insights.