Jobs at Mythic AI

Build and support a robust EDA/CAD environment for IC design teams. Manage PDK, IP, tool, revision-control, licensing, compute-farm, and infrastructure environments. Develop automated EDA flows, scripts, plug-ins, regression systems, and CI/CD pipelines; troubleshoot Linux/Unix, license-server, and tool integration issues; advise leadership on methodology, tooling, and infrastructure upgrades.

Leads corporate IT and DevOps across four international sites, managing teams, SaaS applications, identity, endpoints, networking, datacenter and EDA infrastructure. Owns security, compliance, Linux systems, Kubernetes, CI/CD, developer tooling, physical IT, vendors, budgets and infrastructure modernization. Drives identity automation, OS migrations, SaaS governance, audit readiness, datacenter expansion, international integration and support for semiconductor engineering environments.

Lead end-to-end systems engineering to turn Mythic analog compute chips into validated, customer-ready cards, modules, and platforms. Build and scale validation teams, drive hardware/software co-validation, own test infrastructure and automation, support OEM/hyperscale qualification, and feed field learnings into product and architecture decisions.

Develop and own DSP and algorithm blocks to mitigate analog impairments for analog compute-in-memory: calibration, non-linearity compensation, offset correction, and error estimation. Build Python frameworks and firmware, improve simulation fidelity, correlate silicon and simulation errors, and lead silicon bring-up, characterization, and productization with cross-functional teams.

Lead and build Mythic's marketing function end-to-end: define brand and category narrative, create vertical and product positioning, build demand-generation and sales enablement assets, recruit and scale a full marketing team, and represent the company externally across data center, automotive, robotics, and defense markets.

Own full-cycle recruiting for technical and leadership semiconductor roles. Partner with hiring managers and executives on hiring strategy, compensation, and org design. Source niche passive candidates, manage high-volume confidential and executive searches, drive offers and negotiations, mentor junior recruiters, and improve TA processes and employer branding.

Design, develop, and verify NVM IP and digital controllers for compute-in-memory products. Define controller architecture, build and validate behavioral and RNM models, improve RTL design and verification methodologies, and collaborate with circuit, compiler, firmware, and software teams.

Design and verify complete non-volatile memory (NVM) IP macros and peripheral circuits for product architectures. Optimize NVM architecture for performance and area, develop interfaces with analog compute blocks, run RNM/functional modeling, collaborate on tapeout, silicon debugging, validation, and production qualification.

Design Verification Engineers will develop and verify designs for AI processors, collaborating across teams to ensure functionality through rigorous testing and innovative strategies.

Develop and verify designs for AI processors, focusing on system-level verification, testbench development, and collaboration with RTL designers.

The RTL Design Engineer will design and implement components for next-gen AI processors, collaborate on microarchitecture, and drive timing closure, optimizing for performance and power efficiency.

Architect and build MLIR ecosystems, extending dialects while ensuring conversion paths. Collaborate with hardware engineers to integrate with PyTorch and modern frameworks.

Develop the next generation AI compiler for Mythic's analog compute, optimizing for dataflow architectures and collaborating with hardware engineers.

The role involves verifying mixed-signal and digital systems, creating RNMs, ensuring interface clarity, and contributing to methodologies across teams.

The role involves optimizing analog-aware software for neural networks, designing algorithms, improving software quality, and collaborating on hardware validation. Requires experience with complex algorithms and communication skills.

The Compiler Engineer will design compiler IRs and strategies for complex algorithmic workloads, collaborating with hardware engineers to enhance ISA and execution models, ensuring performance and correctness, while simplifying developer experiences.

The Senior RTL Design Engineer will design and implement components for next-generation AI processors, collaborating with various engineering teams to ensure performance and correctness while focusing on low-power, high-performance designs.

Design and verify NVM IP macros and circuits for Mythics analog compute-in-memory products. Develop RNM/functional models, HV generators, x/y-paths, peripherals, and handshake circuits with analog compute blocks. Lead full-chip simulation, tapeout support, layout supervision, silicon debugging, and coordinate validation and backend teams to qualify production releases.