Jobs at Neurophos

The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.

Design, simulate, and optimize passive silicon photonic components for AI applications, collaborate with foundry partners and cross-functional teams.

Lead the architecture, design, simulation, validation, and commercialization of silicon photonic devices (grating couplers, waveguides, SOAs, photodetectors). Develop link budgets, collaborate with foundries using PDKs, perform DFM/DFT, run optical simulations, characterize devices in lab, integrate with electro-mechanical and software teams, lead design reviews, support IP and patent filings, and mentor junior engineers.

Develop and optimize high-performance Analog IPs for photonic AI platform, perform custom IC layout, and coordinate with designers and EDA vendors.

Lead Security Engineer to design and defend cloud, network, and systems infrastructure. Implement zero-trust, IAM/PAM, SIEM/EDR, vulnerability management, incident response, vendor/customer security assessments, and drive SOC 2 Type II compliance while partnering with engineering and legal.

Lead end-to-end datacenter scale-out networking architecture for the T100 platform: host networking stack to EIC PCIe bridge, NIC integration, and DMA into HBM. Define RDMA/transport/offload (RoCEv2, UET), PCIe P2P/ACS policies, queue/completion semantics, vendor selection, collective communication modeling, DPU roadmap, standards representation, and mentor architecture and software engineers.

Lead and build Neurophos' in-house IT function across Sunnyvale and Austin. Own on-prem Linux compute for EDA/CAD, storage, backup, SSO/IdP (Okta), GitHub Enterprise, cloud (Azure) administration, network design, MSP governance, endpoint fleet management, and insourcing roadmap. Design hybrid connectivity, security/compliance evidence, and scale infrastructure from ~50 to 150+ employees while hiring and mentoring the IT team.

Lead development of inference servers and racks, owning electrical, mechanical, and systems engineering from boards and interconnects through rack-level power and high-speed channel closure. Build and lead the Systems team, drive integration/bring-up, EVT/DVT/PVT sign-off, system reliability (RAS), and manage schedule and budget for full-scale product delivery.

Lead development of a compiler toolchain for a custom LLM accelerator: design IR/graph transformations and lowering passes, optimize compute and memory patterns, integrate with PyTorch/JAX/Triton, build test infrastructure, and ensure correctness and performance for hybrid optical-electronic hardware.