Teams at Neurophos

Lead EDA tooling and physical design infrastructure for analog/mixed-signal IC teams: evaluate and deploy Cadence/Spectre/Calibre toolflows, manage PDKs and TSMC N3P/N2P enablement, architect CAD compute clusters, develop SKILL/Python/Tcl automation, manage licenses/version control, liaise with foundries/vendors, provide hands-on tape-out support, and drive methodology improvements to improve designer productivity and first-pass silicon success.

Lead development of a compiler toolchain for a custom LLM accelerator: design IR/graph transformations and lowering passes, optimize compute and memory patterns, integrate with PyTorch/JAX/Triton, build test infrastructure, and ensure correctness and performance for hybrid optical-electronic hardware.

The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.