Jobs at Sandisk Corporation

Lead enterprise strategy for corporate purpose, employee communities, volunteering, giving, and learning. Own learning ecosystem (LMS/LXP), content strategy, governance, adoption, measurement, and team leadership. Partner with executives and HR to embed purpose into culture, scale volunteering and grants, and ensure programs align to business priorities and workforce readiness.

Design and verify memory systems for HBF-based NAND Flash products targeting AI infrastructure. Develop products, execute HBF stress tests, and verify/characterize HBF management algorithms on real systems.

Lead end-to-end strategic sourcing for engineering lab equipment, IT hardware/software, cloud and security technologies. Manage RFx processes, supplier selection, contract negotiation, supplier performance, risk mitigation, and deliver cost savings while partnering cross-functionally with engineering, IT, legal, and finance.

Lead month-end close and consolidation activities, prepare journal entries and reconciliations, support global accounting processes, drive automation and process improvements, oversee quality reviews and trainings, and assist internal and external audits to ensure SOX and US GAAP compliance.

Lead end-to-end program execution for consumer products: plan, coordinate cross-functional teams, manage timelines/risks, launch products, and implement continuous improvements and post-launch feedback loops.

Lead development and activation of a scalable partnerships and alliances strategy across the Americas. Own strategic partner relationships (imaging, gaming, NAS, licensed brands), negotiate and manage joint business planning, drive co-marketing and retail/e-tail integration, develop experiential activations, manage budgets and measurement frameworks, and mentor cross-functional teams to grow brand, demand, and revenue.

Lead hardware architecture, design, and development of high-performance test and validation platforms. Define system-level architectures, drive technical decisions, oversee PCB/PCB layout and SI/PI, mentor engineers, collaborate cross-functionally (FPGA, firmware, mechanical, manufacturing), and lead bring-up, validation, root-cause analysis, and production release.

Design, build, and maintain finance dashboards and reports (daily to yearly) using BI tools. Extract and analyze financial data with SQL, support budgeting/forecasting, automate recurring reports, ensure data accuracy and governance, and provide actionable insights to finance, accounting, and leadership stakeholders.

Lead supply chain planning analysis and scenario-based planning to balance demand, supply, capacity, and inventory. Develop constraint-based plans, improve forecast accuracy, drive material/resource optimization, support cross-functional reviews, and implement continuous improvement and process standardization using advanced planning systems.

Lead end-to-end technical programs to develop and deploy semiconductor and memory test solutions. Drive cross-functional alignment across design, validation, test engineering, manufacturing and quality; manage schedules, risks, vendors, KPIs, and production readiness to ensure on-time delivery and scalable, high-quality test automation and production test flows.

Design and architect high-speed chip-to-chip and rack-scale interconnects for AI inference infrastructure. Specify fabrics, transport/link protocols, topologies, and optimize bandwidth, latency, power, area, reliability. Collaborate with SoC, package, and software teams and influence industry standards.

Define strategy, roadmap, and execution for next‑generation AI memory products. Drive customer engagements with hyperscalers/chipmakers, translate requirements into MRD/PRD, lead cross‑functional execution (ASIC, firmware, NAND, supply chain), build business cases, and maintain competitive intelligence for AI/high‑performance memory architectures.

Lead enterprise architecture strategy across business and technology domains, modernize application and platform landscapes, establish hybrid/multi-cloud and data/AI platforms, enforce architecture governance, drive API-first/event-driven integration, and translate business strategy into architecture roadmaps to reduce technical debt and enable measurable business outcomes.

Lead global strategic sourcing for semiconductor categories (especially DRAM). Develop and implement commodity strategies, conduct should-cost analysis, negotiate contracts, manage suppliers and performance, monitor market trends, and collaborate cross-functionally to support NPI and procurement objectives.

Serve as finance business partner to Global Procurement, providing financial analysis for sourcing, supplier negotiations, spend management, KPI monitoring, forecasting, and cost optimization to support procurement decisions and drive savings.

Lead design and implementation of SAP S/4HANA RISE Finance solutions. Drive fit-to-standard workshops, define target processes, produce functional designs, oversee configuration, ensure compliance (SOX), coordinate integrations and data migration, support testing and change management, and liaise between business, technical teams, and SI partners for go-live readiness.

Lead architecture of AI/ML accelerator ASICs integrated with AI storage and xPU devices. Define I/O subsystems (UCIe/PCIe/CXL), DMA, memory hierarchies (HBM), NoC, and firmware/software interactions. Author specs, evaluate PPA tradeoffs, collaborate with cross-functional teams, guide pre/post-silicon validation, and optimize systems for large-scale LLM training and inference.

Provide high-level administrative support to senior consumer product leaders: manage complex calendars, coordinate domestic and international travel and visas, organize meetings/offsites, reconcile expenses, prepare and edit presentations, maintain files, and proactively solve operational issues to ensure efficient executive team operations.

Define and author AI/ML accelerator ASIC and AI Storage system architectures (UCIe/PCIe/CXL), specify I/O subsystems and DMA, evaluate PPA tradeoffs, collaborate with RTL/DV/firmware teams, perform LLM workload characterization, and guide pre- and post-silicon validation to optimize performance, power, area, and endurance.

Lead system-level architecture for AI inference and advanced memory solutions, optimize compute/memory bottlenecks, map ML workloads to hardware, drive hardware/software co-design, and provide technical leadership across chiplet, SoC, and memory subsystem designs.