Teams at Velaura AI, Inc.

Own the architecture and technical direction of a heterogeneous AI SoC runtime spanning sensor ingest, preprocessing, inference, postprocessing, and application delivery. Define execution, memory, synchronization, driver, firmware, compiler-runtime, observability, resilience, and validation architectures. Lead cross-functional engineers while contributing hands-on to production systems software, performance optimization, APIs, and low-level interfaces for robotics and edge AI workloads.

Own verification of custom AI accelerator hardware, including matrix and vector engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regressions. Verify numerical precision, quantization, data flow, performance, latency, and power efficiency across RTL blocks and complete systems. Collaborate with architecture, software, compiler, runtime, and systems teams through design bring-up, emulation, and pre-silicon validation.

Own the CAD and engineering infrastructure supporting silicon development, including compute, storage, scheduling, cloud, security, disaster recovery, EDA tools, licensing, and RTL-to-GDS flow releases. Lead CI/CD, regression infrastructure, flow qualification, vendor strategy, and AI-assisted engineering adoption. Ensure scalable, reproducible, secure platforms support concurrent SoC programs and thousands of weekly jobs while partnering with RTL, verification, DFT, physical design, packaging, and software teams.