Jobs at Altera (altera.com)

Own and develop production Reliability Verification tools, flows, automation, regressions, and methodology for custom/analog and ASIC designs. Execute EM/IR analyses, triage violations, support tape-outs, enable new process nodes, and drive fixes to sign-off. Provide user support, documentation, training, and vendor engagement while modernizing RV workflows and applying AI/ML and scripting to improve performance.

Lead strategy, development, deployment, and scaling of custom-analog design automation and AI-assisted workflows. Automate schematic, layout, verification, and signoff processes; apply AI/ML to sizing, layout assistance, and verification triage; establish IP reuse and flow-hardening practices; measure productivity and adoption; partner across fabric, SerDes, and IO teams; and mentor engineers adopting new methodologies.

Lead physical design execution across blocks and full-chip integration from floorplanning through tapeout. Own schedules, quality, risk mitigation, cross-team coordination, critical-path recovery, and signoff alignment. Partner with methodology and CAD teams, resolve execution blockers, engage senior customer stakeholders, and mentor physical design engineers. The role requires hands-on expertise in advanced-node implementation, timing and power closure, signoff flows, scripting, and delivery across complex multi-site designs.

Leads Altera’s AI transformation of hardware design by defining AI/ML strategy, deploying tools across design, verification, and implementation workflows, building data and evaluation foundations, and measuring productivity impact. The role requires deep semiconductor and EDA expertise, hands-on ML/LLM experience, cross-functional influence, vendor evaluation, stakeholder engagement, and mentoring without direct reports.

Drive product definition and roadmaps for PCIe, CXL, and DMA IP for FPGA devices. Gather and prioritize market and customer requirements, align cross-functional programs, generate product requirements, and coordinate engineering execution and change management to deliver hard and soft IP solutions.

Designs, implements, and maintains virtualized infrastructure across Azure Local, Hyper-V, Windows Server, SQL Server, file-sharing, and SUSE Linux environments. Develops PowerShell and Bash automation, administers SCCM deployments and patching, implements monitoring solutions, troubleshoots infrastructure issues, and collaborates with IT teams on secure, scalable hybrid-cloud solutions.

Develop and optimize FPGA firmware, including device configuration and security features, using C and C++. Responsibilities include writing design specifications, unit and system tests, emulator or silicon validation, and collaborating with hardware and validation engineers to debug complex system issues.

Partners with executive and senior leaders to align HR strategies with business objectives. Supports talent management, succession planning, performance management, organizational design, restructuring, employee relations, change management, and organizational effectiveness initiatives. Uses HR analytics, metrics, and AI tools to provide data-driven insights and guide decisions. This individual contributor role is based in the San Jose office four days per week.

Develops and supports automated FPGA and ASIC design verification flows from RTL through GDSII. Responsibilities include building scripting frameworks, integrating and enhancing EDA tools, applying AI/ML to design automation, automating repetitive workflows, improving design infrastructure, and collaborating with design, verification, CAD/EDA teams, and vendors. The role requires extensive experience with front-end RTL, pre-silicon verification, EDA tools, Unix/Linux, Python, Tcl, and Shell.

Develop and maintain C++ and Python software models representing FPGA devices within Quartus Prime. Build high-performance APIs supporting synthesis, placement, routing, timing, and power analysis. Collaborate across hardware and software teams to integrate next-generation FPGA devices and create tools for FPGA device bring-up. The role requires strong software engineering, algorithms, data structures, communication, and experience with EDA or FPGA tools is preferred.

Lead end-to-end FPGA development kit execution across board architecture, RTL, firmware, validation, manufacturing, and supply chain. Coordinate global engineering teams, design partners, ODMs, contract manufacturers, and suppliers. Drive BOM planning, cost optimization, component availability, obsolescence management, technical risk resolution, manufacturing execution, and platform robustness improvements.

Leads static timing analysis methodology and design automation for ASIC, custom, semi-custom IP, and FPGA timing flows. Owns production-grade flow architecture, characterization, regression, validation, deployment, and support. Partners with design, physical design, reliability, technology, and EDA vendor teams; resolves live timing issues through tape-out; evaluates tools and drives methodology roadmaps. Provides technical direction, mentors engineers, and may apply AI/ML to timing and design automation.

Own and scale Workday integrations, reporting, data governance, and workforce analytics. Serve as the Workday subject matter expert, translating business needs into reliable system solutions while partnering with HR, Payroll, IT, Finance, and vendors. Ensure data integrity, operational effectiveness, and actionable workforce insights. Lead integration and reporting strategy, support Workday security and reporting capabilities, and potentially guide teams or technical project delivery.

Provides technical guidance and customer support for Altera FPGA transceiver and protocol IP solutions throughout architecture, implementation, hardware bring-up, validation, and production. Responsibilities include reviewing designs, debugging RTL and hardware issues, reproducing cases with FPGA and lab tools, coordinating defect resolution, developing scripts and reference designs, delivering training, and contributing to product readiness and documentation. The role requires expertise in high-speed serial interfaces, transceiver PHYs, FPGA design flows, protocols, and hardware troubleshooting.

Own end-to-end backend IC design automation flow bring-up for new semiconductor process nodes, including PDK, standard-cell library, Foundation IP, EDA tool, script, and infrastructure integration. Develop regression tests, qualify and deploy production flows, support design teams through tape-out, and provide debugging, training, documentation, and methodology improvements. Collaborate across global engineering teams and apply AI/ML to regression analysis, flow optimization, and knowledge capture.

Leads global equity administration and supports compensation program design, governance, accounting, reporting, controls, and employee experience. Partners with Finance, HR, Legal, Payroll, Tax, executives, and external providers on equity transactions, grants, vesting, ESPPs, executive compensation, valuations, disclosures, tax requirements, and SOX-ready processes. Builds the equity administration team, manages platforms and data integrity, develops analytics, and provides participant education.

Lead design and delivery of end-to-end Salesforce solutions across Sales Cloud, Revenue Cloud and CPQ. Own Lead-to-Quote architecture, build Agentforce/Claude agents, use AI-assisted tools like Cursor, define integrations with ERP, ensure compliance, lead discovery workshops, and support testing, enablement, and stakeholder alignment.

Performs semiconductor failure analysis, electrical fault isolation, and root-cause investigations for FPGA yield, reliability, and customer-return issues. Uses non-destructive techniques including EMMI, LVP, and OBIRCH, along with commercial testers and layout, schematic, and design-analysis tools. Partners with product, yield, reliability, design, foundry, manufacturing, packaging, and physical failure analysis teams to improve product quality and reliability.

Lead end-to-end delivery of web, digital, and marketing-technology projects. Translate business needs into technical requirements, coordinate Marketing and IT, manage plans, schedules, risks, vendors, QA, deployments, and post-launch support. Ensure alignment across stakeholders, integrations, analytics, accessibility, security, and performance for enterprise web initiatives.

Performs semiconductor physical failure analysis to identify root causes of yield, reliability, and customer-return issues. Uses emission microscopy, laser voltage probing, OBIRCH, SEM, FIB, and EDX to isolate failures and analyze materials, devices, layouts, and schematics. Collaborates with product, yield, reliability, design, and process engineers to improve manufacturing yield, performance, quality, and reliability. Develops analysis methodologies, FMEAs, control plans, reports, and corrective actions while supporting new product and package technology transfers.