Jobs at Altera (altera.com)

Design, implement, verify, and optimize synthesizable RTL for FPGA and programmable hardware solutions supporting AI acceleration and Physical AI applications. Develop microarchitectures, datapaths, control logic, and accelerator architectures; support synthesis, timing closure, debugging, hardware-software integration, and system bring-up. Collaborate with architecture, verification, firmware, software, and physical design teams to deliver high-performance, scalable computing solutions for robotics, autonomous systems, machine vision, and edge AI.

Leads annual planning, forecasting, long-range financial planning, financial modeling, variance analysis, executive reporting, investment evaluation, and performance management. Partners with senior leadership and cross-functional teams to guide strategic decisions, resource allocation, IPO readiness, and financial process improvements. Supports board and investor presentations while improving reporting frameworks and forecast accuracy.

Provides hands-on technical leadership for RTL architecture, microarchitecture, implementation, integration, verification, and delivery of FPGA and programmable SoC subsystems. Leads high-performance datapath, memory, interconnect, packet-processing, and acceleration designs while balancing power, area, timing, reliability, and schedule. Establishes RTL methodologies, drives cross-functional technical execution, resolves complex design issues, and mentors engineers across global teams.

Lead architecture, microarchitecture, RTL development, integration, verification support, timing closure, bring-up, and performance characterization for FPGA and programmable SoC subsystems. Translate system requirements into scalable digital designs, drive tradeoffs across performance, power, area, and reliability, and resolve complex cross-functional issues. Establish reusable IP, coding standards, automation, and quality practices while mentoring engineers and influencing technical roadmaps across global hardware, software, verification, and product teams.

Leads functional safety architecture for semiconductor and IP development across avionics, automotive, defense, space, and industrial markets. Defines safety concepts, mechanisms, requirements, and architectures; performs FMEA, FMEDA, FTA, and DFA analyses; guides ASIL/SIL decomposition and verification strategies; and ensures diagnostic coverage and safety certification. Collaborates across hardware, software, design, verification, and external assessment teams to produce safety cases and achieve ISO 26262, IEC 61508, and related compliance.

Develops and validates manufacturing test content for FPGAs to detect defects, improve test coverage and yield, and optimize test time and cost. Responsibilities include DFT strategy, scan insertion, MBIST, ATPG, test pattern development, RTL integration, pre-silicon simulation, silicon failure analysis, customer return investigation, and collaboration with manufacturing and test teams.

Designs, integrates, validates, and debugs FPGA RTL systems for embedded, networking, SmartNIC, and acceleration applications. Responsibilities include integrating PCIe, Ethernet, EMIF, and ARM HPS IP; supporting board bring-up and system validation; developing software abstractions and drivers; collaborating on hardware/software co-development; optimizing performance; and contributing to FPGA-based product architecture, deployment, and customer investigations.

Designs, develops, and secures production-grade generative AI platforms, LLM, RAG, and agentic AI applications. Builds model-serving infrastructure, orchestration frameworks, observability and guardrails, and cloud-native services. Implements AI security, governance, threat modeling, vulnerability remediation, secure deployment, CI/CD, and DevSecOps practices across cloud and hybrid environments.

Develop and operationalize long-range business plans by applying strategic analysis, business judgment, and practical AI expertise. Evaluate AI opportunities, build forecasts and KPI frameworks, solve complex business problems, and translate data into recommendations for senior stakeholders. Partner cross-functionally with finance, product, marketing, sales operations, data, and technical teams while managing ambiguous workstreams and aligning contributors.

Designs FPGA example solutions and technical assets using Quartus tools, supports customers by debugging and resolving design issues, evaluates product features, develops unit tests, and improves customer journeys. The role also creates training materials, AI skills, and agents to accelerate customer design workflows. Requires FPGA design, simulation, debugging, signal analysis, development board, and minimal software experience.

Leads global financial consolidation and reporting across multinational entities, overseeing close processes, intercompany accounting, foreign currency translation, consolidated statements, controls, audits, and process automation. Partners with finance, IT, procurement, tax, treasury, and regional teams to improve reporting quality, compliance, and close predictability while supporting technical accounting initiatives and leading distributed teams.

Supports corporate FP&A through budgeting, forecasting, financial modeling, P&L analysis, variance reporting, dashboard development, and workforce cost tracking. Partners with finance and business stakeholders, responds to ad hoc analytical requests, maintains planning and reporting systems, improves financial processes, and contributes to finance transformation initiatives.

Design and implement DFT architectures for complex semiconductor products, including FPGA, processor, DSP, SERDES, IO, and multi-die designs. Responsibilities include defining specifications, inserting test logic, generating ATPG patterns, applying timing constraints, validating designs pre-silicon, and supporting silicon bring-up and debug. The engineer will collaborate with IP, integration, and test development teams while improving DFT automation, test coverage, manufacturing yield, test cost, and production readiness.

Leads global SOC and incident response operations, including monitoring, alert triage, investigations, detection engineering, escalation, playbooks, metrics, and major incident coordination. The role improves security operations through SIEM, SOAR, EDR/XDR, automation, threat intelligence, threat hunting, and MITRE ATT&CK-aligned detections. It oversees SOC workflows, global handoffs, managed security providers, incident readiness exercises, and cross-functional collaboration while ensuring processes satisfy governance, regulatory, privacy, and audit requirements.

Lead enterprise identity and access management, privileged access management, and data loss prevention programs. Establish security governance, lifecycle controls, privileged account protections, data classification, DLP policies, incident response, compliance reporting, and continuous improvement. Partner with cross-functional teams to reduce security risks, improve control effectiveness, and strengthen enterprise security maturity across corporate systems, cloud environments, sensitive semiconductor data, source code, and intellectual property.

Develops timing methodologies and executes full-chip timing for advanced FPGA products. Responsibilities include timing modeling, integration and validation, clocking and timing constraint development, STA and SPICE correlation, extraction analysis, timing signoff, quality checks, and technical issue resolution. The role collaborates with front-end, back-end, and cross-functional teams to improve timing processes and deliver complex semiconductor designs on aggressive schedules.

Defines and scales security assurance and global compliance practices across engineering and product teams. Establishes SDL requirements, lifecycle checkpoints, controls, evidence plans, and reporting. Conducts security reviews, CRA assessments, readiness reviews, and security hackathons; coordinates certification activities with notified bodies and stakeholders. Supports FPGA customers with security and certification requirements, tracks remediation, validates corrective actions, and reports progress to technical and executive audiences.

Lead complex FPGA device development programs from definition through production rollout. Coordinate silicon, IP, software, firmware, validation, manufacturing, and globally distributed engineering teams. Manage schedules, milestones, dependencies, risks, resource constraints, and critical paths. Improve program management processes, provide executive status reporting, and support silicon bring-up, validation, sampling, and production readiness. Influence cross-functional stakeholders and drive accountability without direct authority.

Lead complex FPGA and semiconductor product development programs from product definition through production. Drive strategy, roadmaps, milestones, risk mitigation, cross-functional alignment, executive reporting, and technical readiness across architecture, silicon, hardware, software, firmware, validation, and manufacturing teams. The role requires influencing distributed engineering organizations, resolving technical and organizational challenges, improving program governance, and mentoring other technical program leaders.

Leads enterprise infrastructure cyber defense across network, cloud, on-premises, hybrid, and engineering environments. Oversees network and cloud security, application security, DevSecOps, vulnerability management, security architecture, risk assessments, cyber resilience, governance, and executive reporting. Partners across Security, IT, Engineering, Compliance, Legal, and Audit to establish controls, improve visibility, reduce vulnerability exposure, strengthen resilience, and develop security capabilities. Requires hands-on leadership across Azure, AWS, infrastructure protection, secure SDLC, and security testing.