Jobs at Altera (altera.com)

Design, implement, and validate BootROM and firmware for FPGA configuration and security. Write firmware specs, implement features in C/C++, create unit/system tests, and validate on emulators or FPGA silicon. Collaborate with hardware and validation teams to debug complex system-level issues.

Develop and deploy ML models and toolchain integrations to optimize FPGA compiler performance (timing, resource use, power). Evaluate ML methods (GNNs, RL), build CI/CD and automation for model conversion/quantization/pruning, benchmark across FPGA families, and collaborate with architects, engineers, and customers to deliver production-ready compiler optimizations.

Lead enterprise compliance for the EU Cyber Resilience Act by translating regulatory obligations into product lifecycle processes, governance, conformity evidence, and metrics. Coordinate cross-functional activities across security, engineering, quality, legal, and product teams; define SBOM and software-component traceability, vulnerability and post-market processes, conformity-assessment frameworks, training, and audit readiness. Monitor regulatory developments and support product classification, technical documentation, and executive reporting.

Lead timing activities for subsystems from implementation through sign-off. Drive block and subsystem timing closure, develop STA methodologies and automation, define I/O timing budgets, run and optimize large MCMM STA, generate/validate ECOs, provide root-cause analysis and timing guidance, and collaborate with RTL, physical design, and full-chip teams.

The Product Development Engineer drives testability and manufacturability of circuits, performs yield analysis using data science techniques, and interfaces with various engineering teams to optimize silicon yield and quality.

The Senior Technical Program Manager will lead complex technical programs for FPGA development, ensuring cross-functional alignment and timely execution throughout the product lifecycle.

Design and deliver mixed-signal/analog IP (regulators, bandgaps, ADCs, DLLs, SerDes) through schematic, pre/post-layout optimization, verification, collateral generation, and post-silicon debug in advanced CMOS processes while collaborating cross-functionally.

Design and ship LLM-powered agentic AI systems and RAG pipelines, build multi-step reasoning workflows, improve model behavior (accuracy, latency, cost), integrate tools and knowledge retrieval, and collaborate on hardware-aware AI optimizations with FPGA/ASIC teams for production platforms.

Lead architecture and development of timing analysis, modeling, and optimization for the Quartus FPGA Compiler. Drive STA, timing closure, MCMM, PBA, timing modeling, and compiler infrastructure improvements. Mentor teams and collaborate across synthesis, placement, routing, and architecture to improve QoR, runtime, scalability, and signoff correlation for next-generation FPGA devices.

Drive thermal and electrical characterization and system-level validation of FPGA products, develop DFT and manufacturing test flows (ATPG, MBIST, BIST), analyze silicon and test data to close tester-to-system gaps, optimize yield and test time, and collaborate across design, packaging, manufacturing, and reliability teams.

The role involves verifying design architectures using UVM methodology, creating test cases, and coordinating with cross-functional teams for full coverage verification.

The Aerospace & Defense Product Program Manager leads cross-functional teams to execute FPGA and platform programs, ensuring compliance with regulatory standards and managing program risks from concept to production.

Lead planning activities for next generation FPGA products, manage cross-functional teams, conduct market analysis, and communicate product roadmaps. Responsibilities include gathering customer requirements and driving innovation in product strategy.

Develop and support advanced design automation flows for digital semiconductors, improve EDA tools, and drive process enhancements.

The Director of Foundry Engineering will lead foundry engagement and manage silicon manufacturing operations to drive yield and reliability for FPGA products while collaborating closely with cross-functional teams.

Design and implement DFT architecture and specifications for complex ICs (FPGA, processor, DSP, SERDES, multi-die). Insert test logic, run ATPG and pre-silicon validation, collaborate with IP/integration and test teams for silicon bring-up, debug, and production readiness. Improve DFT methodologies and automation to meet coverage, cost, yield, and manufacturability goals.

Lead design, verification, and optimization of high-speed interconnects. Develop simulation methodologies using EDA tools for electrical performance. Collaborate across design teams to meet performance goals.

The Staff/Senior Staff NPI Debug Engineer leads critical hardware investigations, orchestrates taskforces to resolve silicon issues, and conducts yield analysis. This role requires in-depth hardware debug expertise and the ability to communicate findings to executive leadership.

Drive product definition and roadmaps for PCIe, CXL, and DMA IP for FPGA devices. Gather and prioritize market and customer requirements, align cross-functional programs, generate product requirements, and coordinate engineering execution and change management to deliver hard and soft IP solutions.

Define and drive silicon domain subsystem architecture for next-generation FPGAs, focusing on security (Root of Trust, secure boot), FPGA configuration, microarchitectural features, hardware/software integration, validation/test planning, modeling and simulation, and cross-functional collaboration to deliver secure, high-performance, and power-efficient silicon solutions.