Jobs at Altera (altera.com)

The Treasury Manager will oversee cash flow forecasting, manage global bank accounts, ensure compliance, and lead automation projects in the treasury department.

Responsible for design validation of high-speed protocol IPs, creating verification plans, developing testbenches, and collaborating with teams for implementation and quality improvement.

The Technical Program Manager leads complex technical programs for FPGA device development, coordinating efforts across various engineering disciplines, managing schedules, and ensuring global team alignment.

As a Senior DFT Design Engineer, you will define and implement DFT architectures, perform test logic insertion, collaborate with design teams, and contribute to DFT methodologies.

Oversee and mentor a GUI development team, coordinating global efforts and collaborating with various teams to deliver EDA tools.

Lead enterprise Quality Management System for FPGA design, ensuring compliance with standards like ISO 9001 and AS9100D. Oversee audits, issue management, and drive continuous improvement.

Design and deliver mixed-signal/analog IP (regulators, bandgaps, ADCs, DLLs, SerDes) through schematic, pre/post-layout optimization, verification, collateral generation, and post-silicon debug in advanced CMOS processes while collaborating cross-functionally.

The Product Development Engineer drives testability and manufacturability of circuits, performs yield analysis using data science techniques, and interfaces with various engineering teams to optimize silicon yield and quality.

The Senior Technical Program Manager will lead complex technical programs for FPGA development, ensuring cross-functional alignment and timely execution throughout the product lifecycle.

The Aerospace & Defense Product Program Manager leads cross-functional teams to execute FPGA and platform programs, ensuring compliance with regulatory standards and managing program risks from concept to production.

Lead planning activities for next generation FPGA products, manage cross-functional teams, conduct market analysis, and communicate product roadmaps. Responsibilities include gathering customer requirements and driving innovation in product strategy.

The role involves verifying design architectures using UVM methodology, creating test cases, and coordinating with cross-functional teams for full coverage verification.

Define sensor-to-actuator Physical AI reference architectures; analyze and partition AI, vision, perception, planning, and control workloads across CPUs, DSPs, FPGA fabric, GPUs, and AI accelerators; develop workload models and benchmarks; drive architecture tradeoffs and influence next-generation SoC, FPGA, memory, interconnect, and accelerator roadmaps.

Develop and support advanced design automation flows for digital semiconductors, improve EDA tools, and drive process enhancements.

The Director of Foundry Engineering will lead foundry engagement and manage silicon manufacturing operations to drive yield and reliability for FPGA products while collaborating closely with cross-functional teams.

Lead design, verification, and optimization of high-speed interconnects. Develop simulation methodologies using EDA tools for electrical performance. Collaborate across design teams to meet performance goals.

The Staff/Senior Staff NPI Debug Engineer leads critical hardware investigations, orchestrates taskforces to resolve silicon issues, and conducts yield analysis. This role requires in-depth hardware debug expertise and the ability to communicate findings to executive leadership.

Design and implement DFT architecture and specifications for complex ICs (FPGA, processor, DSP, SERDES, multi-die). Insert test logic, run ATPG and pre-silicon validation, collaborate with IP/integration and test teams for silicon bring-up, debug, and production readiness. Improve DFT methodologies and automation to meet coverage, cost, yield, and manufacturability goals.

The Senior MLOps & AI Infrastructure Engineer will architect, build, and operationalize ML systems, design ML pipelines, and manage AI infrastructure while collaborating with various teams on best practices.

Lead global teams in semiconductor hardware engineering, focusing on chip package and board development, power and reliability engineering, and strategic vendor management.