The Product Development Engineer develops DFT strategies for FPGAs, collaborates with design teams, implements test plans, and analyzes test results to optimize manufacturing quality.

The Product Owner/Business Analyst will implement an Enterprise Data Warehouse and reporting solutions, collaborating with stakeholders to analyze requirements, design solutions, and ensure data quality.

Provide advanced administrative support to senior staff, manage calendars, coordinate travel, handle confidential information, and assist with project coordination.

Lead global AI engineering team, developing and applying AI/ML solutions for manufacturing. Oversee integration of AI in production processes and ensure data governance.

Assist in all aspects of physical design flow, including synthesis and timing analysis, while utilizing scripting for automation and debugging.

This role involves designing, implementing, and managing virtualized and cloud infrastructures, administering SQL databases, automating processes, and ensuring system performance and security.

The SoC Logic Design Engineer will develop RTL designs for SoC integration, conduct quality checks, optimize designs, and ensure IP-SoC handoff compliance.

The Technical Accounting Manager prepares financial statements, reviews accounting transactions, advises on accounting standards, and collaborates across departments to enhance accounting policies and practices.

The Sr Silicon Design Verification Engineer conducts functional logic verification, develops plans and test benches, runs simulations, debugs issues, collaborates with teams, and improves verification methodologies.

Design and deploy AI/ML solutions to improve manufacturing yield and quality, leveraging data analysis and machine learning technologies across semiconductor processes.

The VP will lead the SerDes Validation team, overseeing strategy, technical validation, team management, and customer engagement to ensure product success.

The Senior Director of Post-Silicon Validation will define validation strategies, oversee the validation lifecycle, collaborate with teams, and lead a validation team to ensure product quality.

The Performance Power Validation Manager leads a team in validating silicon products for power and performance, ensuring quality targets are met through collaboration and management of validation methodologies.

Lead full-chip implementation from RTL to GDSII focusing on timing closure, power optimization, and physical verification while using EDA tools and automation scripts.

Lead the vision and execution of Altera.com digital experience, managing UX, web strategy, and cross-functional teams to align with business goals.

As an FPGA Application Engineer, provide technical support, resolve customer issues, and create collateral for FPGA design using Intel products.

The role involves physical design implementation, power integrity analysis, verification, and optimization of SoC engineering design processes, including mentoring junior members.

The Senior Director leads Altera's global quality strategy for the ADG segment, ensuring compliance with quality standards, managing audits, and driving quality excellence across functions.

The Director, Global Treasury will establish and lead the global treasury function, manage banking relationships, implement cash forecasting, and develop investment strategies to optimize cash management and treasury policies.

Lead the development of FPGA design platform Quartus, delivering front-end EDA tools and enhancing FPGA design through AI technologies. Manage a large engineering team and promote innovation and technical excellence.