Develops and validates manufacturing test content for FPGAs to detect defects, improve test coverage and yield, and optimize test time and cost. Responsibilities include DFT strategy, scan insertion, MBIST, ATPG, test pattern development, RTL integration, pre-silicon simulation, silicon failure analysis, customer return investigation, and collaboration with manufacturing and test teams.
Job Details:Job Description:
For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.
Join us in our journey to becoming the world's #1 FPGA company!
Altera is searching for a Product Development Engineer to join our Manufacturing Content Development Engineering Group!
The Manufacturing Content Development Engineering Group is responsible for architecting, developing, validating and productizing high quality manufacturing test content for FPGAs to screen out any manufacturing defects and thus guaranteeing the highest quality of outgoing parts to customers.
Other responsibilities of the Product Development Engineer include but are not limited to:
- Develop and implement DFT strategies for FPGAs, including scan insertion, BIST (Built-In Self-Test), and test compression techniques.
- Collaborate with RTL design and verification teams to ensure testability features are embedded efficiently.
- Define and implement test plans, patterns, and fault models to ensure optimal test coverage and yield.
- Develop and maintain MBIST manufacturing test content flows and scripts.
- Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out.
- Analyze test results, debug silicon failures, and provide root cause analysis.
- Work with manufacturing and test teams to optimize test time, cost, and quality.
- Analyze early customer returns with emphasis on driving test hole closure activities.
- Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations.
- Stay updated with industry trends and emerging DFT/test technologies.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$106,200 - $153,675 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Qualifications:Minimum Required Qualifications:
Bachelor's or Master's Degree in Electrical Engineering or related field, with 3+ years of industry experience in the following:
- Experience in IC design and IC test.
- Experience in DFT methodologies such as scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG and JTAG networks
- Test development tools (e.g., TessentIJTAG, Tessent MemoryBIST, FastScan, Tessent Shell etc).
- Experience with RTL design, synthesis, and verification flows.
- Experience with fault grading, test time analysis, test coverage analysis, and test yield enhancement.
- Scripting skills in Python, Perl, TCL, or similar.
- Semiconductor manufacturing test processes.
- Digital and analog circuit fundamentals.
Preferred Qualifications:
- Master's Degree in Electrical Engineering, or equivalent (or other related Engineering degree).
- Experience with Tessent MBIST flows for pattern development and knowledge of memory repair schemes and Memory algorithms is a plus.
- Post-silicon experience including pattern conversion, Automated Test Equipment (ATE) pattern bring-up and silicon characterization is a plus.
Altera (altera.com) San Jose, California, USA Office
101 Innovation Dr, San Jose, California, United States, 95134
Similar Jobs
Manufacturing
Leads mechanical product development for Emtek handles and entryways from concept through production. Owns technical planning, risk mitigation, design reviews, DFM/DFA, manufacturing process development, supplier collaboration, failure analysis, and product requirements. Partners with cross-functional teams, communicates technical information to stakeholders, mentors engineers, supports intellectual property development, and drives robust, cost-effective designs. The hybrid City of Industry role requires approximately 15% domestic and international travel.
Top Skills:
3-D CadCfdDfmaDoeFeaFmeaGd&TQfdSolidworksTolerance Stack-Up Analysis
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Own silicon product development from pre-silicon through launch, including ATE test content, product bring-up, characterization, qualification, yield improvement, and test-duration analysis. Manage schedules, manufacturing and assembly partners, foundry and memory vendors, and cross-functional supply and demand programs. Apply expertise in ASIC mixed-signal design, BIST and SCAN DFT, FinFET technology, GPU product engineering, HBM memory, and advanced packaging.
Top Skills:
AsicAteBistChip-On-Wafer-On-Substrate (Cowos)FinfetGpu CharacterizationHbmMixed-SignalScan Dft
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
Drive bring-up of advanced SoCs by analyzing wafer- and package-level ATE failures, identifying yield limiters, characterizing performance and power, and leading cross-functional root-cause and improvement efforts. Collaborate with architecture, software, hardware, test, foundry, quality, customers, and suppliers to enhance test coverage, reliability, and next-generation product development.
Top Skills:
Advanced PackagingAutomatic Test Equipment (Ate)JmpPythonSystem-On-Chip (Soc)
What you need to know about the San Francisco Tech Scene
San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
