Jobs at Broadcom

Lead end-to-end mainframe DevOps architecture for enterprise customers: design blueprints, run design workshops, set standards, mentor consultants, drive migrations to Endevor/Zowe-based CI/CD integrations, support pre-sales scoping, and serve as primary technical escalation while traveling to client sites.

Design and execute block- and chip-level verification for high-speed interconnect ASICs. Build SystemVerilog UVM testbenches, validate IEEE Ethernet protocols, understand chip architecture, and create scripts/tools to improve verification efficiency. Collaborate with architecture, firmware, physical and layout teams throughout product development.

Design and verify front-end RTL blocks for ASIC cores: define architecture, implement logic, perform synthesis, constraints, simulation and formal verification, analyze timing from physical implementation, debug Verilog designs, and collaborate across global teams within the full ASIC implementation flow.

The Nokia Global Account Manager will drive global sales revenue, manage executive relationships, orchestrate internal teams, and expand market opportunities in the Telco sector.

Lead architecture and design of high-performance clocking solutions. Manage full lifecycle of analog timing IPs and validation, ensuring integration into SoCs.

Lead and participate in complex ASIC physical implementations across synthesis, DFT, floorplanning, P&R, clock and power methodology, timing closure, signal integrity, and physical verification using multiple EDA tool flows.

The Verification Engineer will develop verification plans, maintain UVM-based testbenches, analyze simulations, and collaborate with teams to ensure design quality.

Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

Develop and validate ATE test programs and flows on Advantest/Teradyne platforms. Diagnose failures, create characterization tests, support qualification and R&D test methodology, analyze electrical/thermal root causes, and present results to cross-functional teams.

Develop and optimize ATE test programs and test hardware for high-speed networking switches. Debug failures, reduce test time, perform volume data analysis, collaborate with design and production teams, and support extreme temperature ASIC testing.

Design and develop high-performance electronic products while leading a small design team. Own all aspects of hardware design and collaborate with cross-functional teams.

The role involves technology integration for RF ICs, collaborating on technology development and qualification, and managing projects from concept to high-volume manufacturing.

Develop and execute pre-silicon emulation test plans for high-performance networking ASICs. Create tests and synthesizable models, run emulation on platforms like Zebu/Palladium, debug root causes, correlate with post-silicon results, and improve automation and reusable verification components.

The Test Engineer will develop, debug, and maintain test programs for semiconductor testing, collaborate with various teams, and optimize test methodologies.

Contribute to SOC development by architecting verification environments, debugging simulations, writing diagnostics, and utilizing low power silicon verification for mobile applications.

The role involves architecting SOC verification environments, developing test plans, debugging simulations, writing diagnostics for FPGA and ASIC validation, and automating verification flows.

Lead design, simulation, layout, and system testing of silicon photonic integrated circuits using tools like Ansys/Lumerical and Cadence Virtuoso. Collaborate with layout, fab, validation, packaging, and system teams to optimize devices, define process monitoring, and validate link performance. Develop test and qualification plans and perform RF/SI and electrical/optical co-design for high-speed transceivers.

Lead DFT planning and integration using Siemens Tessent. Manage ATPG/ATE interfaces, ATE bring-up and failure analysis. Drive test-time reduction, implement DFT across multi-power domains, and perform synthesis, formal verification, STA and simulation for DFT modes while troubleshooting and improving DFT flows.

Design and develop mechanical assemblies for high-performance electronic products, ensuring compliance with safety regulations and product lifecycle ownership.

Lead qualification, characterization, and transfer of analog/mixed-signal CMOS ICs from proto to volume production. Perform reliability qualifications (ESD, LU, HTOL, package), PVT product characterization, statistical analysis, and reporting. Drive cross-functional projects for release to production, yield improvement, cost reduction, and customer support. Support package/process qualification, failure analysis, and maintain product quality targets.