Jobs at Broadcom

Provides high-level administrative and operational support to the Vice President of Global Operations and department teams. Responsibilities include complex calendar and travel coordination, expense and purchase order processing, onboarding support, event and meeting logistics, facilities liaison duties, office supply management, deadline tracking, confidential information handling, and cross-functional coordination. The role also mentors junior administrative staff and supports executive briefing center operations.

The OS kernel software development engineer will work on ESXi kernel and hypervisor architecture, focusing on CPU and hardware support. Responsibilities include collaboration across teams, hardware enablement projects, and maintaining high quality in solutions.

Designs and delivers mechanical assemblies and full chassis for high-performance power electronic products. Owns mechanical design across the product lifecycle, including BOM creation, DFM, validation, manufacturing transition, production support, customer trials, and field issue resolution. Collaborates with multidisciplinary engineering, manufacturing, sales, compliance, and support teams. Provides technical leadership or mentorship to a small design team and supports complex products from inception through volume production.

Designs and delivers mechanical assemblies and full chassis for high-performance power electronic products. Owns mechanical design across the product lifecycle, including BOM creation, vendor collaboration, product aesthetics, DFM, validation, manufacturing transition, customer trials, field issues, and sustaining engineering. Collaborates with hardware, ASIC, signal, thermal, packaging, manufacturing, and partner engineering teams. May provide technical leadership or mentorship to a small design team.

Support deployment and technical integration of Broadcom Ethernet switching and NIC platforms for HPC and AI/ML data centers. Responsibilities include troubleshooting switching designs, embedded software, SAI and SDK integrations, benchmarking, congestion and QoS tuning, and advising users on RDMA, AI fabric topology, and network performance. The role also requires technical documentation and coordination with customers and internal engineering teams.

Leads cross-functional engineering projects developing RF antenna tuner products for Tier-1 mobile customers. Responsibilities include managing project timelines, resources, risks, and milestones; serving as the primary technical customer contact; and guiding module debugging, impedance and aperture tuning, and RF optimization through mass production.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.

Lead and participate in complex ASIC physical implementations across synthesis, DFT, floorplanning, P&R, clock and power methodology, timing closure, signal integrity, and physical verification using multiple EDA tool flows.

The IC Design Engineer designs and develops integrated circuits, oversees ASIC development, defines architecture, and evaluates processes. Responsibilities include leading product delivery and mentoring junior team members.

Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.

Designs and delivers high-performance electronic products while owning end-to-end electrical hardware development, including BOMs, circuit and board design, validation, manufacturing support, customer trials, field issues, and product sustaining. Collaborates with hardware, ASIC, signal integrity, mechanical, thermal, diagnostic, packaging, manufacturing, and partner engineering teams.

Develop and maintain low-level firmware for ARM-based storage controllers, focusing on RAID functionality and PCIe, NVMe, SAS, and SATA protocols. Responsibilities include feature design, implementation, debugging, log analysis, issue resolution, product validation, release support, and hardware integration. The engineer will troubleshoot firmware-hardware interactions using DSTREAM and logical analyzers and collaborate with hardware and validation teams throughout the development lifecycle.

Drive overall sales revenue for Google, managing relationships and aligning cross-functional teams while expanding Google's networking footprint.

Develops and debugs ATPG and MBIST DFT patterns, supports post-silicon bring-up, and improves wafer sort and final-test yield. Responsibilities include scan diagnostics, failure analysis, repair debug, yield excursion root-cause analysis, silicon characterization, and correlation of electrical failures with fab data. The engineer partners with product and test engineering teams, performs volume data analysis, creates automated dashboards and wafer maps, and uses scripting and AI tools to identify process shifts and improve product yield and cost.

Design, develop, test, debug, and maintain low-level firmware, middleware, applications, diagnostics, and drivers for embedded optical PHY products. Collaborate with system, analog, and digital hardware teams; troubleshoot embedded C code; establish software architecture, coding standards, design patterns, and documentation practices; and help recruit and mentor engineering talent.

Designs high-speed ASIC blocks for 10Gbps–400Gbps communication systems. Responsibilities include architecture, RTL/HDL coding, timing constraints, verification, synthesis, equivalency checking, CDC and lint reviews, power and design-for-test analysis, scripting, silicon bring-up, lab debugging, and production qualification. Collaborates with distributed engineering teams to define resources, schedules, validation plans, and design tradeoffs.

Designs and validates ASIC blocks for high-speed optical communication physical-layer products. Responsibilities include architecture, RTL coding, lint, CDC, synthesis, equivalence checking, timing analysis, simulation, silicon debug, verification planning, power and area tradeoffs, silicon bring-up, and ATE validation. Requires expertise in ARM subsystems, high-speed digital design, Ethernet and OTN networks, FEC, ASIC development flows, and design-for-power, test, and manufacturing.

Executes the full physical IC design cycle from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL design engineers and applies TCL/Perl scripting and EDA tools. This is an in-person role in Colorado Springs, Colorado.

Design and develop analog/mixed-signal integrated circuits for high-speed data communication, perform transistor-level design and layout, investigate architectures, and characterize and debug prototype and production ICs in the laboratory.

Lead DFT programs including specification, implementation, and verification for ASIC products, focusing on various phases of SoC DFT-related activities and customer interactions.