Jobs at Cadence Design Systems

Partners with global R&D leaders and managers to deliver HR guidance, workforce planning, talent programs, performance management, compensation, employee relations, organizational change, and team effectiveness initiatives. Uses workforce data to identify talent needs and recommends actions. Coordinates global HR programs, supports reorganizations and acquisitions, facilitates leadership discussions, and collaborates with regional HR teams and Centers of Excellence.

Provides technical leadership and customer application support for Cadence advanced packaging and 3D-IC solutions. Develops workflows, demonstrations, proof-of-concepts, signoff methodologies, reference flows, and training for 2.5D/3D-IC, chiplet, substrate, interposer, and AI/HPC packaging. Supports customer evaluations and deployments, collaborates with sales on pre-sales engagements, communicates requirements to R&D, and advises on signal integrity, power integrity, thermal analysis, and package design.

Designs and develops analog and mixed-signal CMOS integrated circuits, including SerDes and high-speed I/O systems, from concept and specification through verification. Responsibilities include designing transmitters, receivers, serializers, PLLs, clock-distribution circuits, bias circuits, and voltage regulators; applying jitter and signal-equalization techniques; using CAD tools for simulation, layout, and physical verification; and collaborating with engineering teams.

Lead physical design solutions from synthesis through GDS and tape-out for complex HPC devices. Drive floorplanning, placement, routing, clock construction, timing, power, IR/EM, and physical verification closure. Improve design tools, flows, and methodologies while optimizing power, performance, and area. Collaborate with RTL, DFT, architecture, and R&D teams across advanced technology nodes to deliver high-quality SoC designs.

Develops and maintains Palladium Debug software using C++ on Linux. Responsibilities include new feature development, debugging, testing, performance optimization, and collaborative software engineering. The role requires strong foundations in algorithms, data structures, object-oriented programming, and computational complexity, with opportunities to apply parallel programming, systems knowledge, Electronic Design Automation, and coding AI agents to complex development tasks.

Leads customer-facing digital implementation and signoff initiatives from RTL to GDSII. Responsibilities include synthesis, floorplanning, place and route, timing and power closure, clock tree synthesis, PPA optimization, flow automation, technical presentations, customer support, and collaboration with R&D on Cadence EDA tools and methodologies for advanced-node SoC tape-outs.

Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Responsibilities include customer presentations, workshops, demonstrations, benchmarks, technical evaluations, methodology consultations, solution implementation, account campaigns, customer support, and collaboration with R&D. Requires expertise in timing signoff, advanced-node static timing analysis, constraints debugging, ASIC implementation flows, scripting, and customer-facing communication. Travel is required up to 20%.

Performs static timing, glitch, noise, and SPICE analysis using Cadence Tempus Signoff. Develops timing and ECO flows, validates constraints, benchmarks tool features, and supports advanced OCV/SOCV, PBA, distributed, and concurrent STA methodologies. Collaborates with R&D and customers on timing correlation, in-design ECO optimization, and new technology enablement. Automates workflows with Perl, Tcl, and Python, leads customer signoff campaigns, and delivers technical training.

Leads and develops a high-performing sales team, builds customer pipelines, and delivers booking targets. Consults with clients on IC and system design requirements, architects differentiated EDA, IP, hardware, and design services solutions, and builds executive-level customer relationships. Aligns customer roadmaps with Cadence offerings while coordinating internal technical and business stakeholders. Requires extensive technical sales, engineering leadership, EDA business process, communication, negotiation, and customer consulting experience.

Lead strategic account growth for Cadence EDA, IP, hardware, and design services. Direct worldwide account executive and technical executive teams, coordinate application engineering resources, build sales pipelines, achieve booking targets, and advise executive customers on complex design and business challenges. Develop differentiated solutions, align customer roadmaps, foster executive relationships, and advocate internally for customer requirements.

Lead customer-facing technical engagements for Cadence’s EDA and Agentic AI solutions, optimizing semiconductor design implementation and signoff for advanced nodes. Drive benchmarks, flow customization, synthesis, place-and-route, timing, power, and IR-drop closure. Collaborate with R&D and product teams, influence tool enhancements, lead technical programs, and represent Cadence through industry presentations and technical publications.

Develop advanced bus-routing and constrained-routing algorithms for Cadence Innovus, a semiconductor physical-design platform. Build high-performance, scalable C/C++ software on Linux/UNIX, debug routing issues, and improve runtime, robustness, and quality. Collaborate with R&D teams to define requirements, validate solutions, and deliver production-ready features for advanced digital IC designs.

Leads customer-facing pre-sales and post-sales support for Cadence digital IC implementation and signoff products. Provides expertise in synthesis, place and route, design closure, timing and power signoff, STA, and SDC debugging. Conducts presentations, demonstrations, benchmarks, and technical evaluations; improves implementation flows using Tcl, Perl, and shell scripting; collaborates with R&D; supports business cases; and mentors junior engineers.

Develop algorithms and high-performance C/C++ software for advanced power routing and power optimization within Cadence’s Innovus digital implementation platform. Responsibilities include debugging, performance optimization, quality improvement, and collaborating with cross-functional R&D teams to deliver production-ready semiconductor design features.

Leads U.S. and Canadian indirect tax compliance, including sales and use tax, audits, registrations, returns, and exemption certificates. Owns tax technology initiatives involving tax engines, ERP and billing integrations, product tax mapping, and automation. Improves data quality and reconciliations, maintains SOX controls, supports financial reporting, advises on taxability and pricing, and communicates risks to Finance and Tax leadership.

Define compute-centric SoC subsystems and software stacks for Physical AI, Edge AI, computer vision, audio, robotics, and autonomous systems. Architect hardware and software integration using Cadence IP, optimize power, performance, area, and flexibility, and guide performance modeling, simulation, RTL implementation, firmware, and system integration. Develop proof-of-concept designs, validate software performance, and influence future IP roadmaps. Requires extensive architecture experience and up to 10% international travel.

Lead customer integration and adoption of Cadence interface IP in complex SoC designs. Provide technical authority for system-level IP integration, resolve escalations, develop reference designs and technical documentation, deliver customer training, guide product evaluations, and drive product enhancements. The role requires deep expertise in RTL design, verification, high-speed protocols, AMBA, SoC implementation flows, and cross-functional technical leadership.

Provides desktop support, PC configuration and troubleshooting, device asset management, customer service, documentation, and assistance to local and remote employees. The intern collaborates with local, international, and cross-functional IT teams while learning Microsoft technologies, IT processes, and support procedures. The role is based at the San Jose campus and requires a minimum 12-month commitment.

Certify the Cadence Innovus Platform on advanced foundry process technologies, ensuring performance and reliability. Collaborate with R&D and foundry partners, support customers, and resolve complex physical design, timing closure, and scripting issues using Linux, Tcl, and Python automation.

Develop high-performance C++ compiler software for the Cadence Palladium emulation platform. Apply data structures, algorithms, multithreading, distributed computing, logic optimization, partitioning, and scheduling to solve large-scale compilation problems. Debug and develop software in Linux/Unix environments while working with hardware description languages and electronic design platforms.