Jobs at Cadence Design Systems

Lead and mentor multiple global engineering teams to define and execute the technical roadmap for advanced Static Timing Analysis solutions. Drive scalability, quality, and performance optimization at scale, partner with semiconductor customers and product/executive stakeholders, and foster engineering excellence, talent development, operational efficiency, and customer-centric execution.

Drive development and customer adoption of advanced backend custom IC design flows in Cadence Virtuoso for advanced nodes. Provide customer-facing support: troubleshoot issues, create automation and scripts, collaborate with R&D, and deliver documentation and training to enable efficient layout and signoff flows.

You will design and implement high-performance software while applying machine learning techniques to complex problems in electronic design automation.

Lead software engineer responsible for designing high-level and detailed architectures, performance tuning, and building distributed systems. Work with LLM/ML and big-data technologies (e.g., Langchain, Spark), develop in Python and C++, and design data solutions with strong SQL and database fundamentals. Collaborate across teams and integrate diverse frameworks into practical solutions.

Lead a worldwide account team to drive adoption and growth of Cadence solutions. Build sales pipeline, consult with executive customers on design/system requirements, architect solutions using EDA software, IP, hardware and services, and advocate customer needs across Cadence to ensure long-term success and roadmap alignment.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Drive product engineering for Cadence Genus synthesis solution to improve Power, Performance & Area. Verify new features, perform experiments, debug physical-aware synthesis issues, and ensure interoperability with other Cadence tools. Support field engineers and customers, document product requirements, and bridge synthesis with place-and-route flows.

Lead occupancy and space planning across North American offices and labs. Manage capacity models, stack/block plans, and Moves, Adds & Changes (MAC). Maintain CAFM data, coordinate moves, oversee furniture and space readiness, and report utilization to leadership while partnering with HR, Finance, IT, Facilities, and procurement.

Design and develop analog/mixed-signal IC blocks for high-speed SerDes from concept through verification. Responsibilities include circuit design (drivers, receivers, serializers/deserializers, PLLs, ADC/DACs, biasing, regulators), simulation and layout using CAD tools, lab testing, and collaboration with cross-functional teams.

Prepare quarter-end reporting and audit committee deliverables, validate finance data from SAP/Incorta/CPM/NGA, generate reports and ad hoc analyses, perform data quality reviews and reclasses, support UAT and system enhancements, assist acquisition integrations, and partner with quote-to-cash and cross-functional teams to resolve reporting discrepancies.

The Business Systems Analyst will enhance Salesforce and related systems, optimizing workflows and identifying automation opportunities in a global environment, while collaborating across teams to ensure robust solutions.

The Lead Analog IC Designer will design and develop analog/mixed signal IC circuit blocks, ensure compliance with specifications, and leverage CAD tools for circuit simulation and verification.

The Design Engineering Architect role involves developing PHY architecture, aligning with JEDEC standards, engaging in customer-facing technical support, and collaborating across teams to ensure successful implementation and influence future technology roadmaps.

The role involves designing and testing mixed-signal circuits, contributing to project leadership, and collaborating with the digital team on functional closure.

Provide technical sales support as a senior application engineer for signal and power integrity across IC, package, and PCB designs. Deliver workshops, demos, training, and onsite customer support; analyze customer environments and recommend EDA solutions using Cadence or competitive tools. Collaborate with sales, R&D, product engineering, and marketing to ensure customer success.

Work on Digital Design or Design Verification for the Janus NoC IP: implement and simulate RTL (SystemVerilog), run synthesis/place-and-route flows, develop UVM/SVA tests and verification monitors, debug failures, analyze coverage, and script automation. Collaborate with Design, Verification, and Physical Design teams.

Lead customer technical engagement for Digital/Custom/Analog/RF design flows (Innovus, Virtuoso), drive adoption of advanced layout and AI-driven automation, translate customer needs to R&D, and expand Cadence Custom IC footprint while supporting executive-level discussions and methodology definition.

Provide primary customer and account support for Cadences Palladium Cloud. Manage network and compute configurations, design resilient compute architectures, develop automation/AI tools, perform expert troubleshooting, capacity planning, and manage services like LDAP, Proxmux, and imaging to ensure scalable, fault-tolerant HPC/cloud deployments.

Provide administrative support to HR leadership: manage complex calendars across time zones, coordinate domestic and international travel, organize events and meetings, prepare expense reports and purchase requisitions, support special projects, and handle confidential communications while building cross-functional relationships.

The Principal Product Engineer will develop and drive customer adoption of AI-driven Layout Automation flows, focusing on analog layout expertise and automation technology, while collaborating with customers.