Jobs at Cadence Design Systems

Leads the PLM configuration team and manages product lifecycle data, BOM configurations, component compliance, change control, supply readiness, system integrations, environmental governance, and ISO 9001 procedures. Oversees PLM process improvements, cross-functional collaboration, departmental OKRs, budgeting, reporting, and team development. The role requires extensive configuration management and PLM leadership experience, systems administration expertise, regulatory training, and proficiency with multiple PLM, supply chain, and productivity tools.

Develops high-speed wireline communications transceivers through numerical modeling and architecture. Selects and specifies transceiver components, evaluates end-to-end system tradeoffs, collaborates with analog and digital designers, and supports laboratory characterization of completed designs. The role requires advanced mathematical modeling, communication systems, signal processing, coding, data analysis, signal propagation, circuit knowledge, and experimental skills. The position is based full-time in San Jose.

Provides technical presales, configuration, demonstrations, and customer support for Cadence high-speed SerDes interface IP. Presents IP capabilities, serves as a protocol and product expert, collaborates with sales, marketing, and R&D teams, supports customer opportunities, leads productivity initiatives, and creates technical content. Requires expertise in high-speed protocols including PCIe, CXL, Ethernet, or USB, along with strong presentation and communication skills.

Leads technical presales and customer solutions for Cadence SerDes design IP, including PCIe, CXL, Ethernet, and other high-speed interface PHYs and controllers. Presents product capabilities, configures IP, demonstrates performance, supports customers and field teams, collaborates with sales, marketing, and R&D, and develops technical content. The role also leads productivity initiatives and may require occasional customer-site travel.

Develop and enhance Cadence’s Xcelium RTL/logic simulator and timing-constraint verification technology. Design and optimize graph algorithms for massive SDC constraint graphs, perform C/C++ performance tuning, reduce compilation time and memory usage, write specifications and unit tests, and collaborate with globally distributed engineering teams.

Architect and enhance Cadence’s Xcelium RTL/logic simulator and timing constraints verification technology. Design scalable graph algorithms for multi-billion-node graphs, optimize C/C++ performance and memory usage, develop specifications and unit tests, lead junior engineers, and collaborate with global teams on semiconductor verification software.

Provides senior technical leadership for Cadence Virtuoso heterogeneous integration technologies, including 3D IC, advanced packaging, and multi-die co-design flows. Partners with strategic customers and cross-functional teams to define product strategy, requirements, roadmaps, and technical solutions. Leads customer engagements, validates solutions, prioritizes enhancements, mentors engineers, develops technical collateral, and owns deliverables through customer deployment.

Drives definition, validation, deployment, and adoption of Cadence Virtuoso heterogeneous integration technologies. Partners with semiconductor customers and cross-functional teams to define product requirements, support R&D, troubleshoot design flows, prioritize enhancements, create technical enablement materials, and support launches. The role focuses on 3D IC, heterogeneous integration, advanced packaging, and physical implementation workflows.

Provides technical support for Cadence Palladium, Protium, and Virtual Protocol products. Responsibilities include debugging customer failures, creating replication test cases, coordinating issues with R&D, recommending workarounds, testing fixes and patches, specifying enhancements, and validating new hardware and software features. The role requires expertise in digital design verification, HDL, Unix/Linux scripting, hardware protocols, emulation, and customer communication, with occasional travel.

Provides technical support for Cadence Palladium, Protium, and Virtual Protocol products. Responsibilities include customer performance tuning, compiler feature support, debugging and reproducing failures, testing fixes, developing hardware and firmware expertise, supporting escalations, specifying enhancements, testing new features, and updating training materials. The role collaborates with customers, field account executives, and R&D teams and may require occasional travel of up to 10%.

Provides technical support for Cadence Palladium, Protium, and Virtual Protocol products by handling customer cases, reproducing issues, reporting bugs, testing fixes, and tracking quality metrics. Collaborates with customers, field applications engineers, and R&D teams. Requires digital design and verification expertise, HDL proficiency, Unix/Linux scripting, EDA debugging knowledge, and familiarity with emulation, verification methodologies, and PCIe, USB, or Ethernet protocols. Occasional travel may be required.

Provides technical support for Cadence Palladium, Protium, and Virtual Protocol products. Debugs customer-reported failures, creates reproducer test cases, coordinates issues with R&D, recommends workarounds, tests fixes and patches, supports enhancement requests, and evaluates new hardware and software features. Requires expertise in digital design, verification methodologies, HDL, Unix/Linux scripting, hardware protocols, emulation, and complex EDA environments. Occasional travel may be required.

Develop and validate software for physical verification of advanced semiconductor devices. Solve complex mathematical and geometric problems, maintain reliable engineering applications, collaborate with global R&D teams, participate in code reviews, and improve development processes for next-generation chip design and manufacturing technologies.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.

Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.

Develop and improve UPF compilation software for Palladium and Protium platforms, focusing on performance, correctness, IEEE 1801 support, low-power verification flows, and documentation. Collaborate with R&D, PE, and AE teams to deploy UPF solutions across emulation and prototyping workflows. Contribute to compiler unification, self-checks, example-driven validation, and support for SystemVerilog, Verilog, and VHDL-based designs.

Lead development of low-power verification software for Cadence Palladium and Protium platforms. Responsibilities include enhancing UPF debugging, event logging, violation detection, IEEE 1801 support, documentation, AI-assisted debugging tools, and unified workflows across emulation and prototyping environments. The role requires collaboration with R&D, product engineering, and applications engineering teams, along with strong debugging, C++ code comprehension, RTL language knowledge, technical writing, and communication skills.

Supports FastSPICE technology development, product validation, simulation test execution, and customer issue resolution. The role analyzes transistor-level circuit simulation problems, reproduces and debugs technical issues, validates product features and performance, documents findings, and communicates solutions across engineering teams. Candidates need semiconductor and MOS transistor-level circuit knowledge, SPICE or FastSPICE experience, strong analytical skills, and an engineering degree with 0–4 years of relevant experience depending on education level.

Build and manage sales pipelines for Design IP technology across North American accounts. Drive market penetration, adoption, revenue, and strategic sales plans while managing complex $1M+ licensing deals. Collaborate with engineering, marketing, legal, finance, executives, and EDA sales teams. Develop customer relationships from startups to enterprises, articulate IP value propositions, negotiate contracts, meet revenue targets, and provide market feedback to product leadership.

Develop and troubleshoot multithreaded, distributed physical synthesis software for Cadence’s Innovus platform. Collaborate with global R&D teams, product engineering, and technical sales to deliver customer solutions and workarounds. The role requires C/C++ development in Linux, strong data structures and algorithms knowledge, and customer communication skills. Experience with physical synthesis, timing analysis, multithreading, IC physical design tools, design closure, physical design flows, Tcl, and scripting is preferred.