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Cadence Design Systems

Principal Application Engineer

Posted 7 Days Ago
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In-Office
San Jose, CA, USA
127K-237K Annually
Senior level
In-Office
San Jose, CA, USA
127K-237K Annually
Senior level
Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Responsibilities include customer presentations, workshops, demonstrations, benchmarks, technical evaluations, methodology consultations, solution implementation, account campaigns, customer support, and collaboration with R&D. Requires expertise in timing signoff, advanced-node static timing analysis, constraints debugging, ASIC implementation flows, scripting, and customer-facing communication. Travel is required up to 20%.
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Job Description

We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support. 


Position also involves:

•    Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff).

•    Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns

•    Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations

•    Ongoing support and usage proliferation at existing customers (on/offsite)

•    Working closely with R&D on tools and methodology improvements

•    Create and contribute technical content for Cadence Online Support

•    Travel as required (up to 20%)


The Position Requirements are…

  • Minimum BS-EE plus 8 to 10 year’s experience or MS-EE, plus 6 to 8 year’s experience, Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
  • Digital Design Fundamentals, Semiconductor fundamentals and  Static Timing Analysis is required
  • Experience with ASIC digital implementation flows and tools
  • Working knowledge of a scripting language TCL/Perl/Python
  • Candidate should have strong customer-facing communication and problem solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Strong verbal and written communication skills

The annual salary range for California is $127,400 to $236,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

Cadence Design Systems Santa Clara, California, USA Office

Santa Clara, United States

Cadence Design Systems Sunnyvale, California, USA Office

Sunnyvale, United States

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