Jobs at Lumilens

Lead development, qualification, and supplier management for FR4/PCB substrates. Drive DFM/DFT, quality control, failure analysis, reliability testing, and engage in packaging production processes and supplier risk mitigation.

Develop and execute test solutions across characterization, wafer sort, and final test for silicon photonics and semiconductor products. Build ATE test programs (Advantest/Teradyne), optimize test flows for coverage/time/cost, analyze yield data, debug failures, and collaborate with design, product, and operations to enable NPI and high-volume manufacturing.

Lead full-chip and block-level physical implementation for advanced-node ASICs (5nm/3nm), owning floorplanning, placement, CTS, routing, signoff, and power/timing closure while collaborating with RTL, STA, IP, and verification teams to resolve high-speed transceiver implementation challenges.

Lead process development for III-V etching, coating, and related fabrication modules; translate product requirements into process specs and control plans; define tooling and metrology; design and run DOEs to optimize yield and manufacturability; qualify vendors and tools; document and institutionalize processes; collaborate with device, packaging, manufacturing, and external fabs to troubleshoot and scale.

Design and implement front-end digital RTL blocks (SystemVerilog) including high-speed datapath, UCIe adapters, FIFOs, and assertions. Develop micro-architecture, write block-level testbenches, ensure lint/CDC/timing cleanliness, collaborate with DV/backend, and support simulation, emulation/FPGA bring-up and silicon debug.

The Director of Silicon Test Engineering will lead test strategy and execution for silicon photonics products, optimizing test solutions and ensuring product reliability. Responsibilities include managing ATE test development, driving yield optimization, and collaborating with cross-functional teams while building a high-performing engineering team.

The role involves designing and optimizing advanced packaging solutions for ASICs, conducting FEA simulations, and collaborating with cross-functional teams to enhance photonics technologies for AI and high-performance computing.

As an IC Package FEA Engineer, you will conduct FEA simulations for advanced packaging solutions, optimize designs, and collaborate with cross-functional teams to enhance reliability and performance in photonic devices.

Lead software integration for high-speed optical transceivers on advanced switch architectures, ensuring automation and system debugging, collaborating with cross-functional teams.

Lead signal integrity analysis for photonic-electronic systems, collaborating with design teams to optimize high-speed data paths and package stack-ups.

Lead end-to-end process design, automation, and continuous improvement across NPI, supply chain, manufacturing, and post-sale support. Drive process discovery, future-state architecture, automation specs, KPI dashboards, governance forums, and change management to improve cycle time, quality, and cost outcomes.

The Director of System Applications Engineering will lead a team for deploying optical transceivers, oversee technical engagement, and resolve complex system issues, influencing product decisions and managing customer relationships for AI networking platforms.

Lead the development of packaged silicon photonics solutions, translating customer needs into technical requirements, while driving cross-functional execution and validation.

The Senior Technical Program Manager oversees silicon tapeouts, advanced packaging, and system integration, ensuring timely delivery while managing schedules and stakeholder communications.

Design and deliver high-performance analog/mixed-signal circuits, collaborating with various engineering teams for silicon validation and optimization.

Lead FP&A and revenue management for the US R&D lab, ensuring budget oversight, financial reporting, and strategic planning. Partner with sales and drive automation in finance processes.

Lead supplier strategy and sourcing for silicon photonics, advanced packaging, and optical components. Own supplier selection, negotiations, contracts, cost optimization, risk mitigation, NPI-to-HVM transitions, and supplier performance management. Collaborate with engineering, operations, and finance to align supply with product roadmaps and scale manufacturing.

Build a pre-silicon SystemC/TLM-2.0 virtual platform (ISS-backed MCU, peripherals, UCIe transactor) that runs real firmware. Perform architecture and performance modeling (latency, throughput, buffer sizing), deliver golden reference and behavioral mixed-signal/analog models for DV, and partner with FE architects and firmware leads to align models, RTL, and firmware for early bring-up.

Lead front-end micro-architecture and own the high-speed datapath connecting UCIe to the optical front end. Define RTL coding/CDC standards, timing- and floorplan-aware partitioning, clock/reset and low-power schemes, verification expectations, DFT/debug hooks, and IP integration. Mentor and grow the front-end team and collaborate with backend, DV, and modeling leads to achieve multi-hundred-Gbps physical closure and verifiable architectures.

Lead power integrity architecture and analysis for 2.5D/3D heterogeneous packages integrating electrical and photonic ICs. Perform PDN modeling, simulation, lab validation, component selection, and cross-functional co-design to minimize noise, IR drop, and reliability risks for AI/HPC accelerators through sign-off to production.