Jobs at Lumilens

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.

Provides first-line T1 and T2 helpdesk support across macOS, Windows, and Linux. Responsibilities include ticket triage, device imaging and deployment, onboarding and offboarding, identity administration, connectivity troubleshooting, hardware asset management, conference room AV support, and maintaining IT documentation. The intern will also collaborate on endpoint management, SaaS administration, identity access management, and security initiatives.

Build and own data pipelines, models, quality checks, dashboards, and visualizations for manufacturing and test data. Partner with optical, manufacturing, and quality engineers to create reliable data solutions, improve pipeline performance and cost, and support engineering and leadership decisions. Establish software engineering practices for data systems, guide technical direction across distributed sites, and mentor other engineers.

Owns strategy and execution for high-speed optical interconnect product lines, including co-packaged optics, 800G, and 1.6T transceiver platforms. Coordinates engineering, manufacturing, suppliers, quality, supply chain, sales, finance, and operations to drive product development, validation, launch readiness, customer adoption, and production transfer. Responsibilities include market and competitive analysis, customer engagement, technical trade-off evaluation, roadmap execution, risk management, business cases, and leadership reporting.

Lead development of packaged silicon photonics and optical interconnect products from requirements through validation and production. Define product requirements, analyze optical links, coordinate engineering and external partners, guide packaging and assembly execution, and establish testing strategies. The role requires hands-on laboratory work, customer and supplier engagement, cross-functional leadership, and attention to manufacturability, reliability, thermal performance, and scale-up readiness.

The Director of Silicon Test Engineering will lead test strategy and execution for silicon photonics products, optimizing test solutions and ensuring product reliability. Responsibilities include managing ATE test development, driving yield optimization, and collaborating with cross-functional teams while building a high-performing engineering team.

The role involves designing and optimizing advanced packaging solutions for ASICs, conducting FEA simulations, and collaborating with cross-functional teams to enhance photonics technologies for AI and high-performance computing.

As an IC Package FEA Engineer, you will conduct FEA simulations for advanced packaging solutions, optimize designs, and collaborate with cross-functional teams to enhance reliability and performance in photonic devices.

Lead software integration for high-speed optical transceivers on advanced switch architectures, ensuring automation and system debugging, collaborating with cross-functional teams.

The Director of System Applications Engineering will lead a team for deploying optical transceivers, oversee technical engagement, and resolve complex system issues, influencing product decisions and managing customer relationships for AI networking platforms.

Lead the development of packaged silicon photonics solutions, translating customer needs into technical requirements, while driving cross-functional execution and validation.

The Senior Technical Program Manager oversees silicon tapeouts, advanced packaging, and system integration, ensuring timely delivery while managing schedules and stakeholder communications.

Design and deliver high-performance analog/mixed-signal circuits, collaborating with various engineering teams for silicon validation and optimization.

Lead end-to-end process design, automation, and continuous improvement across NPI, supply chain, manufacturing, and post-sale support. Drive process discovery, future-state architecture, automation specs, KPI dashboards, governance forums, and change management to improve cycle time, quality, and cost outcomes.

Lead FP&A and revenue management for the US R&D lab, ensuring budget oversight, financial reporting, and strategic planning. Partner with sales and drive automation in finance processes.

Lead supplier strategy and sourcing for silicon photonics, advanced packaging, and optical components. Own supplier selection, negotiations, contracts, cost optimization, risk mitigation, NPI-to-HVM transitions, and supplier performance management. Collaborate with engineering, operations, and finance to align supply with product roadmaps and scale manufacturing.

Build a pre-silicon SystemC/TLM-2.0 virtual platform (ISS-backed MCU, peripherals, UCIe transactor) that runs real firmware. Perform architecture and performance modeling (latency, throughput, buffer sizing), deliver golden reference and behavioral mixed-signal/analog models for DV, and partner with FE architects and firmware leads to align models, RTL, and firmware for early bring-up.

Lead front-end micro-architecture and own the high-speed datapath connecting UCIe to the optical front end. Define RTL coding/CDC standards, timing- and floorplan-aware partitioning, clock/reset and low-power schemes, verification expectations, DFT/debug hooks, and IP integration. Mentor and grow the front-end team and collaborate with backend, DV, and modeling leads to achieve multi-hundred-Gbps physical closure and verifiable architectures.

Lead power integrity architecture and analysis for 2.5D/3D heterogeneous packages integrating electrical and photonic ICs. Perform PDN modeling, simulation, lab validation, component selection, and cross-functional co-design to minimize noise, IR drop, and reliability risks for AI/HPC accelerators through sign-off to production.

Manage and coordinate multiple projects, vendors, and facility needs; maintain trackers, prepare status reports, assist with procurement and invoice reconciliation, and serve as liaison across facilities, engineering, IT, procurement, and external vendors to keep project deliverables on schedule.