Jobs at Majestic Labs AI

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Design and optimize high-performance compute kernels for AI primitives (GEMM, attention, convolution), profile and tune across heterogeneous hardware, collaborate with compiler/runtime teams (Triton, PyTorch, SYCL), prototype precision formats, and contribute micro-architecture feedback while writing reusable C++/CUDA/Triton/MLIR code.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Design, implement, and optimize compiler components for AI workloads using PyTorch, Triton, LLVM, and MLIR. Build IRs, codegen passes, and performance-tuned kernels for CPUs, GPUs, and custom accelerators. Contribute upstream to open-source projects and collaborate cross-functionally to enable scalable, high-performance deployment across diverse hardware.

Lead end-to-end technical programs across compiler, kernel, runtime, hardware integration, and data center deployment. Translate system architectures into schedules, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to deliver production-ready server solutions.

Own and optimize the end-to-end LLM serving stack on Majestic hardware: port frameworks (vLLM/SGLang), implement batching, scheduling, paged KV cache, distributed inference, multi-modal preprocessing, speculative/prefix decoding, profile and eliminate bottlenecks across runtime, compiler, and hardware.

Lead architecture and end-to-end firmware design for server platforms, including OOB management, power and thermal control, boot sequencing, firmware update pipelines, and firmware security. Collaborate with silicon and hardware teams, drive silicon bring-up, produce architecture/spec documents, and enforce secure firmware practices.