Jobs at Majestic Labs AI

Design and optimize high-performance AI compute kernels for GEMM, attention, normalization, convolution, and related primitives. Improve throughput, latency, memory behavior, and precision across heterogeneous hardware. Integrate kernels with Triton and PyTorch, profile workloads using performance tools, evaluate mixed-precision formats, and collaborate with compiler, runtime, and hardware teams on ISA and memory architecture co-design.

Own full-cycle recruiting across business and R&D functions, including proactive sourcing, candidate screening, pipeline management, interview coordination, offer closing, and candidate experience. Partner with hiring managers, track recruiting metrics, and support early People Operations initiatives such as onboarding and employer branding. The role requires on-site work in Los Altos five days per week and collaboration across global time zones.

Designs and implements hardware and software security architectures for AI inference systems. Owns hardware root of trust, secure boot, confidential computing, isolation, embedded firmware security, model protection, and threat modeling. Leads security features from architecture and emulation through deployment and remediation, collaborating across hardware, software, and research teams. Requires extensive hardware security, silicon, embedded systems, low-level firmware, and security engineering experience.

Own the end-to-end LLM serving stack on custom accelerator hardware. Port and optimize frameworks such as vLLM and SGLang, implementing scheduling, continuous batching, KV caching, distributed inference, multimodal processing, and inference-time optimization. Profile production systems, identify bottlenecks across APIs, runtimes, kernels, and compilers, and guide hardware and software development.

Own strategic sales for a next-generation AI infrastructure company, targeting hyperscalers, frontier AI labs, neoclouds, and large enterprises. Lead technical, multi-stakeholder sales cycles; close major infrastructure agreements; shape go-to-market strategy, pricing, partnerships, forecasts, and customer evaluations. Build the sales organization, establish CRM and deal processes, and relay customer requirements to product and engineering teams. Extensive domestic and international travel is required.

Design, develop, and optimize compiler components for AI workloads across CPUs, GPUs, and custom accelerators. Enhance PyTorch Inductor, Triton, LLVM, and MLIR toolchains; create custom intermediate representations, code-generation passes, and optimization strategies; tune computational kernels for performance; and contribute to open-source compiler projects.

Manage vendor backend execution and NPI for data-center AI chips, coordinating schedules from RTL freeze and physical implementation through tapeout, post-silicon characterization, qualification, validation, and high-volume production. The role bridges hardware design, backend implementation, DFT, and product engineering while challenging technical trade-offs and driving cross-functional execution.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Lead the architectural design of SoC networking, SmartNIC/NIC and switch interface IPs for AI accelerators. Define scale-up/scale-out topologies, hardware offloads for collective operations, optimize transport protocols and congestion control, run performance modeling and simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead architecture and end-to-end firmware design for server platforms, including OOB management, power and thermal control, boot sequencing, firmware update pipelines, and firmware security. Collaborate with silicon and hardware teams, drive silicon bring-up, produce architecture/spec documents, and enforce secure firmware practices.

Lead product definition and delivery for an AI compiler and runtime platform: own compiler/toolchain roadmap, framework integrations (PyTorch, JAX, vLLM, Hugging Face Optimum), kernel optimizations, scale-out orchestration (SLURM, Ray, LMCache), and developer UX to enable optimized execution on Majestic's Ignite APU.