Jobs at Majestic Labs AI

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead strategy and execution for silicon, IP, and system partnerships. Cultivate vendor relationships, manage RFQs, negotiate complex technology and sourcing deals, establish supply chain agreements, and align partnerships with engineering and product priorities while interfacing with founders and leadership.

Lead definition and implementation of the SoC management subsystem for an AI accelerator: integrate ARM cores, PCIe, DDR/LPDDR, peripherals, debug/trace infrastructure, and design control/interrupt/driver interfaces while coordinating RTL, firmware, verification, and board teams to meet performance, power, and area targets.

Design and optimize high-performance compute kernels for AI primitives (GEMM, attention, convolution), profile and tune across heterogeneous hardware, collaborate with compiler/runtime teams (Triton, PyTorch, SYCL), prototype precision formats, and contribute micro-architecture feedback while writing reusable C++/CUDA/Triton/MLIR code.

Provide high-level executive support to founders (calendar, travel, expenses, correspondence) while managing office operations, vendor relationships, facilities, HR logistics, budget oversight, event planning, and new-hire onboarding for a 25–50 person startup.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Design, implement, and optimize compiler components for AI workloads using PyTorch, Triton, LLVM, and MLIR. Build IRs, codegen passes, and performance-tuned kernels for CPUs, GPUs, and custom accelerators. Contribute upstream to open-source projects and collaborate cross-functionally to enable scalable, high-performance deployment across diverse hardware.

Build and operate developer infrastructure: CI/CD pipelines, dev environments, containerized builds, internal deployments, observability, and production-representative dev systems to accelerate engineers across compiler, runtime, kernel, and hardware teams.