Jobs at Majestic Labs AI

Lead go-to-market and enterprise sales for custom AI infrastructure. Own the full sales cycle, technical validation, benchmarking, TCO modeling, contract negotiation, procurement, ecosystem evangelism, strategic partnerships, and outbound pipeline generation. Engage hyperscalers, datacenter operators, AI labs, and quantitative trading firms while translating hardware and software capabilities into customer performance and cost advantages. Define sales playbooks, pricing models, and GTM strategy for an early-stage company.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.

Verify chip-level and performance behavior of custom ASICs: design end-to-end test flows with architecture team, run simulation-based verification, implement UVM environments, use constrained-random and functional-coverage methodologies, and coordinate vendors/contractors.

Provide high-level executive support to founders (calendar, travel, expenses, communications) and manage office operations, vendor relationships, facilities, budgets, onboarding, and culture-building events for a 25-50 person startup.

Lead the architectural design of SoC networking, SmartNIC/NIC and switch interface IPs for AI accelerators. Define scale-up/scale-out topologies, hardware offloads for collective operations, optimize transport protocols and congestion control, run performance modeling and simulations, and produce architecture specifications while collaborating across silicon, firmware, and software teams.

Lead end-to-end technical programs across compiler, kernel, runtime, hardware integration, and data center deployment. Translate system architectures into schedules, manage cross-team dependencies and suppliers, run planning ceremonies, surface risks, and maintain project documentation and roadmaps to deliver production-ready server solutions.

Lead end-to-end signal and power integrity for high-speed interconnects across architecture, pre-silicon modeling, silicon bring-up, validation, and high-volume manufacturing. Perform channel modeling, EM/field solver correlation to lab measurements, PDN analysis, and SI/PI co-design. Support debug, define design rules with cross-functional teams, lead DVT/PVT to production, and improve internal methodology and tooling.

Lead architecture and end-to-end firmware design for server platforms, including OOB management, power and thermal control, boot sequencing, firmware update pipelines, and firmware security. Collaborate with silicon and hardware teams, drive silicon bring-up, produce architecture/spec documents, and enforce secure firmware practices.

Lead product definition and delivery for an AI compiler and runtime platform: own compiler/toolchain roadmap, framework integrations (PyTorch, JAX, vLLM, Hugging Face Optimum), kernel optimizations, scale-out orchestration (SLURM, Ray, LMCache), and developer UX to enable optimized execution on Majestic's Ignite APU.

Lead product strategy and execution for AI accelerator platforms, custom silicon, and server systems. Write PRDs and technical specifications, prioritize features, manage schedules and releases, and coordinate across silicon, hardware, software, AI research, operations, and executive stakeholders to deliver production-scale AI infrastructure.