Jobs at MatX

Lead integrated NPI lifecycle for rack- and board-level AI systems, coordinating CM/JDM partners, PLM/BOM/ECO control, factory test deployment, quality and yield metrics, and high-volume ramp readiness while reporting risks and readiness to executives.

Develop and sign-off performant silicon from RTL to GDSII across blocks, subsystems, and full-chip. Lead partitioning, floorplanning, synthesis, P&R, clocking, verification, timing/power sign-off, and collaborate with Design, Verification, and DFT teams to meet tapeout milestones.

Design and implement compilers for proprietary hardware architecture, focusing on midend and backend development, while providing hardware insights.

The Executive Operations Coordinator supports the CEO and Chief of Staff by managing the CEO's calendar, communications, meeting logistics, and operational projects, ensuring smooth workflow and productivity for the leadership team.

The Architect will oversee hardware architecture, collaborate with teams, and enhance silicon design performance for AI models.

Develop and execute Rust tests to verify silicon designs and software, ensuring they conform to specifications by identifying discrepancies before production.

Develop and maintain performance models of hardware, while collaborating with architecture and runtime teams. Optimize performance and contribute to architectural reviews.

Lead the design of next-generation AI-focused silicon by translating product requirements into SoC architectures and collaborating with teams on power and performance trade-offs.

As a SOC Integration Engineer, you will develop and integrate SOC RTL designs, collaborate with cross-functional teams, and ensure high-quality silicon integration.

Lead the design and architecture of AI-focused SoC systems, defining specifications, driving power-performance-area trade-offs, and collaborating with cross-functional teams on system integration.

As a Senior/Staff Emulation Engineer, you will define and execute emulation strategies, debug connectivity SoCs, and develop reusable automated flows across hardware, software, and system validation.

Responsibilities include contributing to verification methodology, creating testbenches for silicon validation, and driving reviews on verification progress.

The AI Runtime System Software Engineer will design and implement system software components, optimize ML workloads, and collaborate with hardware teams, requiring strong Linux and C programming experience.

The Bluespec Design Engineer will develop silicon designs using Bluespec and Haskell, focusing on performance and reusable libraries for hardware architecture.

As a Runtime Engineer, you will build and manage the host-side interface library, design custom-kernel ABI, and develop Python bindings while also improving LLM inference serving stacks. You'll collaborate on device memory management, runtime overhead, and performance targets.

Lead power architecture for server-class AI accelerators: define budgets, models, and estimation frameworks; correlate architecture to implementation; partner with architecture/RTL/PD/firmware/platform teams; surface cross-functional power tradeoffs; define power-control, throttling, and telemetry to guide implementation.

Design and deliver high-performance silicon subsystems from micro-architecture through sign-off. Own subsystem or chip-level RTL, collaborate with verification, DFT, and physical design teams, drive reviews, achieve area/timing closure, and ensure performance-power-area targets for ASIC/SoC products.

Lead power estimation, modeling, and analysis for AI accelerator SoCs. Perform RTL/gate/post-layout power analysis, build energy models, identify power-reduction opportunities across SoC subsystems, drive optimizations with architects and physical design teams, and develop automation and dashboards to accelerate analysis and sign-off.

Build infrastructure, tooling, and a Rust-based simulator; implement host-side interface libraries; write targeted and randomized tests to exercise corner cases; collaborate with hardware, architecture, and software teams to turn specifications into testable properties.

Drive verification from architecture/design to production silicon by developing scalable methodology, creating testbenches and portable tests, executing subsystem and full-chip verification, achieving coverage closure, and leading reviews toward sign-off, tapeout, and silicon bring-up.