Own AI Cloud strategy and roadmap to showcase hardware advantages, define served models and pricing/tokenomics, write technical PRDs, drive cloud features for enterprise inference, incubate solution architectures, and align product with sales and partner motions to accelerate deals.

The Process/Quality Engineer will enhance manufacturing processes, ensure product quality, and drive compliance while collaborating with cross-functional teams to support new product launches and continuous improvement initiatives.

As a Senior AI Systems Performance Engineer, optimize and scale foundation models, enhance performance across various system layers, and deliver high-performance AI applications.

Lead the architecture and implementation of cloud-based AI inference services, focusing on monetization strategies, systems design, and cross-functional collaboration.

The Principal Compiler Engineer will lead compiler engineering, optimizing ML model performance and coordinating with development teams to innovate compiler infrastructure.

As a Senior Cloud SRE, you'll ensure the reliability and performance of our AI inferencing service, handle incident management, and optimize cloud infrastructure and resource utilization.

The ML Features Solutions Engineer will develop, optimize, and deploy core machine learning features for enterprise applications while collaborating with cross-functional teams to ensure production-grade quality and performance.

You will enhance the performance and reliability of SambaNova's AI inference platform, collaborating with teams to develop and maintain backend components in Python, Go, and Rust, while building testing frameworks.

The role involves leading compiler engineering, innovating compiler infrastructure and optimization algorithms for ML performance, and working with various teams to implement solutions.

Drive planning and execution of multiple software and ML workstreams, manage cross-functional dependencies, gather requirements, track schedules, support development-to-deployment, and improve processes to deliver customer product releases.

Design and implement SystemVerilog RTL for high-speed ASIC compute, memory, and networking subsystems. Define microarchitecture, optimize Power/Performance/Area, collaborate with verification/physical teams, prototype features with architects/software, mentor junior engineers, and improve design flow using AI and automation.