Jobs at SambaNova Systems

Own the end-to-end SambaCloud experience for developers, partners, and managed customers. Lead the experience roadmap across onboarding, APIs, documentation, integrations, demos, and user journeys while partnering with Product and Engineering on platform, infrastructure, security, and reliability priorities. Coordinate technical delivery, releases, readiness, metrics, playbooks, and cross-functional stakeholder communication to ensure reliable, polished cloud experiences.

Develops technical partner marketing strategies across the AI ecosystem, defining joint value propositions and translating integrations into reference architectures, demos, content, launches, and field enablement. The role coordinates Alliances, Engineering, Product, Developer Relations, Sales, and external partners to execute go-to-market programs, support technical workshops and events, create scalable playbooks, and measure developer adoption, partner engagement, influenced pipeline, and customer outcomes.

Support three senior leaders across Engineering, G&A, and Sales by managing complex calendars, meetings, travel, expenses, communications, events, action items, vendors, and confidential information. Coordinate cross-functional processes, track follow-ups and OKRs, assist with organizational planning, and support ad hoc projects in a fast-paced technology environment.

As a Software Architect, you will define the SambaStack platform's technical direction, ensure system scalability, and resolve architectural challenges while mentoring engineers.

Owns architecture, microarchitecture, RTL design, integration, and implementation of high-speed I/O and memory subsystems for AI accelerator platforms. Responsibilities include SystemVerilog development, front-end design flows, protocol and vendor IP integration, PPA optimization, timing closure, verification collaboration, issue resolution, and cross-functional lifecycle execution from architecture through silicon.

Leads ecosystem strategy for SambaNova’s AI accelerator products across networking, inference serving, storage, caching, prefill, CPU offload, and compiler systems. Defines build-versus-partner decisions, owns reference architectures and certification programs, drives co-optimization with software and model partners, and converts ecosystem relationships into deployments, demand, and revenue. The role also leads external positioning, analyst engagement, executive scorecards, and cross-functional execution with engineering, product strategy, marketing, and partners.

Leads competitive intelligence and product strategy for AI accelerator infrastructure. Builds TCO, tokenomics, capacity, and demand models; tracks competitor architectures, roadmaps, supply signals, and data-center systems; translates findings into roadmap, pricing, positioning, and investment decisions. Develops agentic AI tooling to automate research monitoring, specification extraction, and executive briefings. Runs weekly, monthly, and quarterly intelligence cadences for product and executive stakeholders.

Own full lifecycle recruiting for semiconductor hardware engineering roles, including design verification, ASIC/RTL design, physical design, and PCB/systems engineering. Partner with hiring managers to define roles, build pipelines, design interviews, source passive silicon talent, coordinate feedback, close candidates, and maintain recruiting data and metrics in Greenhouse.

Drive planning and execution of multiple software and ML workstreams, manage cross-functional dependencies, gather requirements, track schedules, support development-to-deployment, and improve processes to deliver customer product releases.

Develop and enhance runtime stack features for high performance ML applications, manage system software, and collaborate with teams to optimize AI systems.

Lead development and optimization of the compiler stack for ML systems, collaborate across teams, integrate and deploy products, map ML operations to hardware, and drive compiler infrastructure innovation and performance debugging.

The role involves leading a software engineering team focused on AI infrastructure and enterprise software, ensuring technical quality and team development while also contributing as a hands-on engineer.

Own and operate a global AI inferencing platform: ensure uptime, low-latency performance, scalability and cost efficiency. Build monitoring, alerting, CI/CD, IaC, autoscaling, capacity planning, incident response, and participate in a shared on-call rotation to maintain 24/7 service reliability.

Designs end-to-end data center reference architectures integrating SambaNova hardware and networking. Supports customer deployments, business development, demonstrations, proofs of concept, technical project management, troubleshooting, training, and product feedback. Requires deep networking expertise, system-level knowledge spanning Linux, kernel drivers, PCIe, NICs, and hardware architecture, plus customer-facing presentation skills. Travel is required approximately 30% of the time.

Design and implement RTL components for AI accelerator ASICs from microarchitecture through tape-out and silicon bring-up. Responsibilities include writing and debugging SystemVerilog, optimizing power, performance, and area, supporting synthesis and timing closure, and applying lint, CDC, LEC, and assertion-based quality checks. The engineer collaborates with architecture, verification, and physical design teams while contributing to compute datapath, on-chip network, and memory subsystems.

Own microarchitecture and synthesizable SystemVerilog RTL for major AI accelerator blocks from specification through tape-out. Drive power, performance, and area optimization, timing closure, synthesis, STA, lint, CDC, LEC, assertions, and verification collaboration. Partner with architecture and software teams on performance improvements, advance EDA automation, lead design reviews, and mentor engineers.

Leads end-to-end design verification for next-generation machine learning ASICs through tape-out and first-silicon bring-up. Owns verification architecture, methodology, coverage, performance validation, emulation, FPGA prototyping, debug, schedules, and tape-out readiness. Manages and grows an experienced team of 8–10 engineers, including principal-level staff, while partnering with architecture, design, software, compiler, runtime, hardware, and systems teams.

Design and implement block- and SoC-level DFT architectures for complex AI accelerator chips. Develop ATPG, MBIST, scan, JTAG, IEEE 1500, and IJTAG infrastructure; automate insertion, pattern generation, coverage analysis, and debug; support DFT timing closure, ATE deployment, silicon bring-up, diagnosis, failure localization, yield analysis, and manufacturing test optimization.

As a Senior Cloud SRE, you'll ensure the reliability and performance of our AI inferencing service, handle incident management, and optimize cloud infrastructure and resource utilization.

Develop and execute verification plans for complex AI chip control and initialization features. Build SystemVerilog and UVM environments, tests, assertions, checkers, and coverage models. Verify sequencing, state transitions, clocking, recovery, and cross-domain interactions. Debug simulation and regression failures, analyze coverage, identify root causes, and drive verification closure while collaborating with architects, RTL designers, firmware engineers, and verification teams.