SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
The team integrates SambaNova's AI accelerators into rack scale systems and gets them deployed in customer datacenters. We handle the racking and stacking of tightly integrated network, power, and compute equipment in both prototype and production environments, and we take rack solutions through prototyping into mass production so they stay manufacturable and serviceable at scale. We work with architects, engineering teams, customer datacenter teams, sales, and marketing, and we manage vendor relationships to line the equipment up with our current and future roadmap.
We are looking for a Senior / Lead VLSI Design Engineer to serve as the architect and hands-on owner for various global circuit areas including custom clocking, low-power design technqiues and power distribution integrity while championing chip-level PLL, IO, ESD, and Latch-Up strategy and Integration. In this role, you will design and optimize ultra-low-jitter, low-skew and low-power custom clock distribution networks from the ground up as well as in-depth power analysis and developing low power solutions. Utilizing your deep hands-on background in PLL, ESD, Latch-Up, and IO design, you will partner with specialized IP teams to ensure seamless SoC integration and drive full chip compliance across strict performance and reliability targets.
Key Responsibilities- Architect, design, and perform transistor level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks (H-trees, grids, meshes or hybrid topologies)
- Perform comprehensive signal integrity (SI), power integrity (PI), jitter, skew, and EM/IR analyses across all chip-level clock distribution networks
- Involved in low-power design methodology and power analysis of key components
- Power distribution integrity analysis
- Collaborate closely with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis (CTS) guidelines
- Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures specified by the ESD/Latch-Up methodology
- Drive pre-silicon chip-level reliability and clock timing sign-off before tape-out and support for post silicon bring-up.
- Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics.
- 8+ years of custom analog/mixed-signal VLSI design experience in advanced process nodes (FinFET / GAA, e.g., 7nm, 5nm, 3nm, 2nm).
- Experience designing custom clock networks, low-power design techniques, and custom IO/ESD/Latch-Up circuits.
- Deep knowledge of physical layout requirements for high-speed clocking, parasitic extraction, and low-resistance interconnects.
- Strong cross-functional collaboration and technical communication skills to bridge chip architecture with specialized IP deliverables.
- Experience with Transistor-level circuit simulators, Transmission Line Theory, Jitter and Skew analysis/methodology, PERC, ESD, EM/IR analysis, and parasitic extraction tools.
- Deep familiarity with leading semiconductor foundry ESD and Latch-Up design rules, guard-ring guidelines, and sign-off flows across advanced nodes.
- MS/Ph.D. in Electrical Engineering with experience on custom Analog/Mixed-Signal IC Design or silicon reliability.
- 10+ years of industry experience with a track record of driving complex top-level silicon integrations.
- Experience leveraging modern AI tools and AI-assisted workflows to write scripts (e.g., Python, TCL, SKILL) for flow automation, productivity enhancement, and simulation post-processing
Base Salary Range:
Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
SambaNova Systems Palo Alto, California, USA Office
Our Palo Alto office is in a tech complex known for incubating research facilities and borders the Bay Trail along the Don Edwards Wildlife Refuge. Only a 5-minute walk, our employees often fly out of PAO for lunch with colleagues or enjoy happy hour at the nearby Palo Alto Country Club.
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