Jobs at Samsung Semiconductor, Inc.

Develop and optimize trace-driven power and thermal simulation engines. Integrate IP-level power macromodels, workload traces, thermal solvers, and reduced-order models into scalable simulation flows. Manage time-indexed simulations, generate transient power maps, analyze spatiotemporal hotspots, and ensure performance, scalability, and reproducibility. The role requires strong C++ software engineering, simulation framework development, debugging, software design, and performance optimization expertise.

Designs and verifies high-speed analog and mixed-signal circuits for memory I/O interfaces, including data converters, PLLs, and SERDES. Owns circuit and system specifications, guides layout and floor planning, performs simulations with advanced EDA tools, documents results, and supports silicon bring-up and automated measurement. The role requires expertise in high-speed interfaces, clock distribution, CMOS technology, PPA tradeoffs, scripting, and collaboration with device, process, verification, and layout teams.

Leads hardware emulation for mixed-signal networking SoCs, including platform bring-up, infrastructure and model maintenance, performance debugging, waveform analysis, and methodology enhancement. Collaborates with emulation vendors and simulation, firmware, software test, and hardware design teams to validate chips pre-silicon, support software bring-up, and reproduce silicon failures on emulators.

Leads end-to-end SRAM circuit design for advanced semiconductor nodes, including memory arrays, bit cells, sense amplifiers, decoders, control circuits, custom layouts, and physical verification. Optimizes power, performance, area, and yield through simulation and variation analysis. Develops design automation methodologies, supports test planning and silicon bring-up, mentors engineers, performs silicon debug, and contributes to patents and technical publications.

Leads memory sales strategy and revenue growth by analyzing customers, markets, competitors, demand forecasts, and production allocation. Develops sales plans, manages key customer relationships, supports sourcing activities, coordinates internal resources, identifies new customers, and contributes to long-term agreements, bids, and risk management. The role is based onsite in San Jose, California.

Designs next-generation high-speed I/O digital and mixed-signal interfaces for Samsung AI platforms. Responsibilities include HSIO PHY IP development, high-speed serial protocol design, digital-on-top development flows, collaboration with analog and system teams, signal and power integrity modeling, SoC protocol integration, DFT methodologies, and Ethernet PMA/PMD/PCS technology.

Lead HR measurement and people analytics: design KPI/scorecard frameworks, blend internal workforce and external labor-market data, deliver executive-ready analyses and dashboards, analyze surveys, build self-service analytics, and apply AI to automate and scale insights.

Build and operate production-like AI environments for agentic workflows, distributed inference, disaggregated serving, and MoE deployments. Collect traces and telemetry, analyze workload performance across software and hardware layers, identify bottlenecks, and evaluate multi-node scaling behavior. Define benchmarking methodologies and communicate findings to hardware architects, systems engineers, and software researchers. Provide technical direction for workload characterization and performance evaluation across AI platforms.

Design and develop high-performance PLL and clock-generation circuits for RF transceivers, SerDes, and high-speed I/O applications. Responsibilities include designing PLL building blocks, system modeling, noise and jitter analysis, transistor-level verification, Monte Carlo simulation, silicon correlation, mixed-signal calibration logic, layout guidance, and laboratory characterization of prototypes. Collaborate with digital, layout, and systems teams to deliver power-, area-, and performance-optimized PLL IP.

Develops large-scale interactive web-based visual analytics and profiling tools for AI/ML workloads. Builds visualizations for massive telemetry datasets, partners with compiler and hardware teams, and improves workflows for diagnosing machine learning performance bottlenecks. The role requires extensive experience with data visualization, developer tools, profiling systems, computing architectures, and technical user experience design.

Executes enterprise SSD qualification testing in customer systems, coordinates test plans with internal and customer engineers, investigates failures, performs root-cause experiments, verifies fixes, supports field issue resolution, improves test coverage, and identifies automation opportunities. The role requires system-level testing or development experience with enterprise servers and storage, storage protocol expertise, server debugging, performance analysis, and scripting.

Design and validate high-speed SerDes transceiver architectures and analog circuits using advanced CMOS processes. Responsibilities include schematic development, simulation testbench creation, power and reliability optimization, supervision of layout designers, LVS/DRC validation, and silicon performance validation. The role focuses on low-power, high-speed interconnects for display, camera, UCIe, Ethernet, and related interfaces.

Designs RF/analog PLLs, clock-generation circuits, and SerDes analog PHYs in advanced CMOS technologies. Responsibilities include mixed-signal system modeling, circuit-level verification, production support, collaboration with digital and software teams, critical layout, and prototype lab testing. The role requires extensive experience with frequency synthesizers, PLL subsystems, IC design tools, hardware description languages, physical layout, and laboratory evaluation.

The Associate Manager, Public Relations will lead U.S. media relations, develop earned-media strategies, build journalist relationships, pitch stories, coordinate press events and launches, and support crisis communications. The role partners with internal teams to maintain consistent messaging, tracks media coverage and campaign performance, prepares reports for senior management, and advances brand awareness and business objectives. Daily onsite presence in San Jose, California is required.

Supports sales representatives, headquarters, and customers by managing orders, pricing, shipments, accounts receivable, credit issues, RMAs, samples, invoices, and customer returns. Aggregates sales forecasts for demand planning, enters and invoices orders through SAP, coordinates with logistics and warehouses, resolves discrepancies, and prepares management reports. The role requires daily onsite presence in San Diego, California.

Design and develop high-performance PLL and clock-generation circuits for RF transceivers, SerDes, and high-speed I/O applications. Responsibilities include PLL building-block design, system modeling, noise and jitter analysis, transistor-level verification, silicon correlation, mixed-signal calibration logic, critical layout guidance, and laboratory characterization of silicon prototypes.

Leads memory market intelligence by building analyst and partner networks, gathering market signals, analyzing supply and demand trends, developing scenario models, and translating findings into executive-ready narratives. Partners with sales and marketing teams across AI, server infrastructure, PC, and consumer markets. Uses AI tools to synthesize multi-source data and tracks market share, pricing, and inventory trends. Requires substantial semiconductor industry experience and daily onsite work in San Jose.

Leads SSD enablement, qualification, validation, and production readiness for NVIDIA, AMD, and other AI platforms. Coordinates customer and internal engineering teams to resolve hardware, firmware, PCIe/NVMe, thermal, power, performance, and interoperability issues. Identifies emerging AI storage workloads, conducts feasibility studies and proof-of-concepts, evaluates ecosystem trends, and develops future product opportunities.

Leads storage industry standardization across NVMe, NVMe-oF, OCP, and SNIA; influences committees, drafts specifications, develops patents, and aligns hyperscaler requirements with Samsung SSD controller and firmware roadmaps. The role collaborates with cloud providers and internal R&D, monitors competitive standards activity, supports compliance testing, and produces customer-facing technical education materials.

Lead Samsung’s enterprise and datacenter storage technology roadmap by influencing NVMe, OCP, and SNIA standards. Draft technical specifications, represent Samsung in industry committees, secure patents, translate hyperscaler requirements into SSD controller and firmware features, and align internal R&D with compliance and product goals. Collaborate with major cloud providers on next-generation storage architectures, monitor competitors, and develop technical marketing and customer education materials.