Jobs at Samsung Semiconductor, Inc.

Lead software-hardware co-design to optimize LLM and agentic AI inference. Profile and optimize model execution for memory bottlenecks, influence memory and accelerator architecture, and develop/benchmark inference and serving solutions using PyTorch and vLLM while mentoring teams on best practices.

The Director of Design Verification will oversee SoC verification processes, manage engineering teams, and collaborate across departments to enhance memory and storage capabilities, ensuring first-pass silicon success.

Develop verification infrastructure for AI accelerator IP blocks, create testbenches, mentor junior engineers, and debug across teams.

The role involves developing advanced location technologies, optimizing receiver models, designing algorithms for GNSS systems, and collaborating with various engineering teams. Responsibilities include simulation, testing, and performance analysis of location IP products.

Design and simulate high-speed analog and mixed-signal circuits (PLL, SERDES, data converters), own circuit/system specs, guide and supervise layout, collaborate with verification and process teams, perform silicon bring-up and scripted measurements, and document results to meet PPA targets.

Develop and optimize memory centric computing systems; troubleshoot hardware issues, collaborate with engineers, and stay updated on AI/ML advancements.

Provide hands-on DRAM application engineering support: validate and troubleshoot memory on server platforms, perform SI/PI and timing measurements, run joint customer validations and self-qualification, develop experiments and automation tooling, communicate findings, and coordinate with internal R&D and external teams to resolve memory/system issues.

Develop and support host interface firmware for enterprise SSDs. Analyze, debug, and resolve firmware, system, driver, and interoperability issues at customer sites and development centers. Perform OEM specification gap analysis, customize features, implement firmware patches, inspect customer tests, and collaborate with globally distributed engineering teams. The role requires extensive embedded C/C++ development, storage protocol expertise, hardware debugging, and need-based domestic and international travel, including stays of several weeks.

Develop and support enterprise and data center SSD products by analyzing the full PCIe stack from PHY through Transaction layers. Own link training, LTSSM behavior, enumeration, equalization, flow control, replay, error handling, and data integrity. Debug and optimize PCIe issues across Gen1–Gen7 during product bring-up and sustaining, support compliance testing and PCI-SIG events, and provide onsite customer support. The role requires collaboration with hardware teams and vendors and up to 25% travel.

Provides executive and administrative support through calendar management, travel coordination, expense reconciliation, visitor logistics, bilingual Korean-English communication, and documentation maintenance. Manages R&D budgets, procurement, lab assets, software licenses, business requests, onboarding, offboarding, resource allocation, workshops, and cross-functional action items. Serves as a primary administrative contact for an AI/ML engineering organization and supports operational efficiency across Finance, Procurement, HR, IT, and facilities.

The Senior Account Memory Sales Manager will lead key AI infrastructure accounts, focusing on High Bandwidth Memory solutions, manage executive relationships, and drive commercial activities.

Lead SoC-level microarchitecture, top integration, logic design and RTL implementation for memory/storage controllers. Integrate and review 3rd-party IPs (UCIe, DDR, CPU, Ethernet), collaborate with verification and physical design teams on synthesis, timing, DFT, CDC, lint, and silicon bring-up to deliver production-ready silicon.

Lead U.S. accounting for semiconductor sales and R&D, overseeing financial reporting (IFRS/US GAAP), month/quarter/year close, audits, ICFR, fixed assets/AUC, treasury, AP/P2P, ERP optimization, HQ liaison, and team development to support strategic decisions and compliance.

The role involves managing sales strategies, analyzing market data, improving customer relations, and executing revenue maximization plans.

The role involves adapting PyTorch for specific hardware, building kernel DSLs, designing scheduling passes, and contributing to open-source projects related to AI/ML workloads.

Serve as a strategic Learning and Development advisor to senior leaders, diagnosing capability gaps and designing customized enablement solutions. Build and deliver curricula, workshops, e-learning, toolkits, and AI-enabled learning experiences for Sales, Marketing, and Staff organizations. Facilitate programs, manage vendors and SMEs, promote adoption, measure outcomes, and continuously improve solutions using stakeholder feedback and data.

Own end-to-end physical implementation of memory-centric computing IP and SoC partitions from RTL netlist through GDSII. Drive PPA convergence, timing closure, floorplanning, power delivery, placement, CTS, routing, STA, physical verification, and signoff on advanced process nodes. Collaborate with RTL, verification, foundry, and library teams while automating implementation flows with Tcl, Python, Perl, and AI tools.

Build and maintain large-scale hardware emulation and FPGA prototyping platforms for memory-centric computing SoCs. Partition complex ASIC/SoC designs, develop transactors and SCE-MI co-emulation environments, model memory and I/O interfaces, enable pre-silicon firmware and software bring-up, and run AI/ML workloads. Automate emulation flows, debug hardware and software issues, optimize platform trade-offs, and collaborate with engineering stakeholders to deliver validated designs.

Leads technical marketing and customer-facing design-in activities for semiconductor SoC products, including connectivity, modem, processor, and platform solutions. Manages customer accounts and programs, coordinates engineering, sales, and marketing teams, translates customer requirements into technical solutions, resolves issues, reports to executives, conducts market research, and develops strategic customer relationships across US and global teams.

Develops RTL and HLS IP for memory-centric computing systems supporting AI/ML workloads. Responsibilities include optimizing performance, power, and area; designing memory controllers, NOC, and interconnect IP; collaborating on verification and test plans; debugging hardware; making architecture trade-offs; and supporting SOC integration and stakeholder delivery.