Jobs at Samsung Semiconductor, Inc.

The Senior Staff Engineer will design and develop memory centric computing systems, optimize performance, and collaborate with software engineers while staying current with advancements in AI/ML technologies.

The candidate will define verification strategies, develop test benches, and ensure the functionality of AI accelerator modules, collaborating closely with architects and design engineers.

Design low-power RF and Analog circuits, lead design verification, collaborate with digital teams, and conduct research on advanced wireless techniques.

Lead product marketing for High Bandwidth Memory and Graphics Memory in North America, driving strategy, team management, and market influence while collaborating globally.

Design and develop firmware for enterprise SSD products, debug and optimize code, support customer adoption, and participate in advanced storage development projects.

The Senior Director will oversee Samsung's PDK technical enablement, support product creation, manage design enablement teams, and work with EDA vendors.

Develop verification infrastructure for AI accelerator IP blocks, create testbenches, mentor junior engineers, and debug across teams.

The Senior AI Systems Engineer will design and optimize high-performance Triton kernels for LLM workloads, improve performance efficiencies, and collaborate on hardware-software co-design with teams.

The Director will manage a Customer Qualification team for enterprise SSDs, ensuring high-quality qualifications, interfacing with customers, and overseeing engineering efforts to resolve issues.

The role involves managing enterprise server infrastructure, executing SSD qualifications and tests, triaging failures, communicating with team leads, and identifying automation opportunities.

The role involves developing advanced location technologies, optimizing receiver models, designing algorithms for GNSS systems, and collaborating with various engineering teams. Responsibilities include simulation, testing, and performance analysis of location IP products.

The Staff Engineer, FPGA will design and optimize RTL for FPGAs, manage command queues, ensure cache coherency, and collaborate on system integration and debugging efforts.

The Director of Design Verification will oversee SoC verification processes, manage engineering teams, and collaborate across departments to enhance memory and storage capabilities, ensuring first-pass silicon success.

Design and simulate high-speed I/O analog-mixed circuits, guide layout optimization, and ensure specifications for performance and functionality.

Lead the strategy and operations of OCP S.A.F.E. for Enterprise and Data Center SSDs, ensuring project delivery, vendor management, and collaboration across engineering teams.

Develop and optimize memory centric computing systems; troubleshoot hardware issues, collaborate with engineers, and stay updated on AI/ML advancements.

Lead end-to-end SRAM memory circuit design for advanced nodes, optimizing performance, power, area, and yield. Perform circuit simulation, custom layout, physical verification, automation scripting, silicon bring-up support, mentor junior engineers, and contribute to SRAM methodology and publications.

Manage customer selection of DRAM-based memory solutions, ensuring technical program management, customer relationships, and engineering support while working with internal and external stakeholders.

The Senior Manager, Technical Marketing focuses on custom SoC business development, technical requirements review, customer engagement, and cross-functional collaboration with internal teams for strategic solutions. They build customer relationships and manage account activities, requiring a blend of technical expertise and business acumen.

Lead SoC-level microarchitecture, top integration, logic design and RTL implementation for memory/storage controllers. Integrate and review 3rd-party IPs (UCIe, DDR, CPU, Ethernet), collaborate with verification and physical design teams on synthesis, timing, DFT, CDC, lint, and silicon bring-up to deliver production-ready silicon.