Teams at Tensordyne

Lead ASIC front-end physical design and workflow development for generative AI inference chips. Optimize block-level and full-chip implementation using Cadence and Synopsys tools, including synthesis, formal checks, power analysis, and static timing analysis. Support backend design activities involving clock trees, routing, DRC, LVS, metal fill, and artwork release. Collaborate with global ASIC, design, and verification teams while developing scalable, high-performance EDA workflows.

Lead full-chip and block-level ASIC static timing analysis, timing closure, signoff, and workflow development for generative AI accelerator products. Develop hierarchical constraints and SDCs for high-speed interfaces and multi-clock domains, analyze clocking and routing issues, generate timing ECOs, and improve Cadence/Synopsys-based physical design flows. Collaborate with global ASIC design and verification teams as a hands-on technical leader.

Leads strategic technical engagements for an AI inference platform from architecture evaluation through benchmarking, model enablement, deployment, and production rollout. Builds and manages a high-performing solutions engineering team, guides customer evaluations and deployments, translates customer requirements into product priorities, and develops scalable technical go-to-market assets. Requires deep expertise in AI inference, accelerator architecture, distributed systems, serving frameworks, performance optimization, and customer-facing technical leadership.